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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.35.4.2 2003/12/05 00:05:03 lampret
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// Static exception prefix.
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//
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// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
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// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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// Added embedded memory QMEM.
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//
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//
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// Revision 1.35 2003/04/24 00:16:07 lampret
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// Revision 1.35 2003/04/24 00:16:07 lampret
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// No functional changes. Added defines to disable implementation of multiplier/MAC
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// No functional changes. Added defines to disable implementation of multiplier/MAC
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Line 748... |
// Exceptions
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// Exceptions
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//
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//
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//
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//
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// Exception vectors per OR1K architecture:
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// Exception vectors per OR1K architecture:
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// 0xP0000100 - reset
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// 0xPPPPP100 - reset
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// 0xP0000200 - bus error
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// 0xPPPPP200 - bus error
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// ... etc
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// ... etc
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// where P represents exception prefix.
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// where P represents exception prefix.
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//
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//
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// Exception vectors can be customized as per
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// Exception vectors can be customized as per
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// the following formula:
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// the following formula:
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// 0xPMMMMNVV - exception N
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// 0xPPPPPNVV - exception N
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//
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//
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// P represents exception prefix
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// P represents exception prefix
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// MMMM represents middle part that is usually 16 bits
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// wide and starts with all bits zero
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// N represents exception N
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// N represents exception N
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// VV represents length of the individual vector space,
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// VV represents length of the individual vector space,
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// usually it is 8 bits wide and starts with all bits zero
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// usually it is 8 bits wide and starts with all bits zero
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//
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//
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//
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//
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// MMMM and VV parts
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// PPPPP and VV parts
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//
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//
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// Sum of these two defines needs to be 24
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// Sum of these two defines needs to be 28
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// (assuming N and P width are each 4 bits)
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//
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//
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`define OR1200_EXCEPT_MMMM 16'h0000
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`define OR1200_EXCEPT_EPH0_P 20'h00000
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`define OR1200_EXCEPT_VV 8'h00
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`define OR1200_EXCEPT_EPH1_P 20'hF0000
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`define OR1200_EXCEPT_V 8'h00
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//
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//
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// N part width
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// N part width
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//
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//
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`define OR1200_EXCEPT_WIDTH 4
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`define OR1200_EXCEPT_WIDTH 4
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| Line 874... |
Line 875... |
`define OR1200_SPROFS_BITS 10:0
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`define OR1200_SPROFS_BITS 10:0
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//
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//
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// Default Exception Prefix
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// Default Exception Prefix
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//
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//
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// 1'b0 - 0x0000_0000
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// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
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// 1'b1 - 0xF000_0000
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// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
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//
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//
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`define OR1200_SR_EPH_DEF 1'b0
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`define OR1200_SR_EPH_DEF 1'b0
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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//
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//
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