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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.35.4.5 2004/01/15 06:46:38 markom
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// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
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// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
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// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
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// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
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//
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//
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// Revision 1.35.4.3 2003/12/17 13:43:38 simons
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// Revision 1.35.4.3 2003/12/17 13:43:38 simons
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// Exception prefix configuration changed.
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// Exception prefix configuration changed.
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Line 928... |
//
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//
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// Define it if you want DU implemented
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// Define it if you want DU implemented
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`define OR1200_DU_IMPLEMENTED
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`define OR1200_DU_IMPLEMENTED
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//
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// Define if you want HW Breakpoints
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// (if HW breakpoints are not implemented
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// only default software trapping is
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// possible with l.trap insn - this is
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// however already enough for use
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// with or32 gdb)
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//
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//`define OR1200_DU_HWBKPTS
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// Number of DVR/DCR pairs if HW breakpoints enabled
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`define OR1200_DU_DVRDCR_PAIRS 8
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// Define if you want trace buffer
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// Define if you want trace buffer
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// (for now only available for Xilinx Virtex FPGAs)
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// (for now only available for Xilinx Virtex FPGAs)
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`ifdef OR1200_ASIC
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`ifdef OR1200_ASIC
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`else
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`else
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`define OR1200_DU_TB_IMPLEMENTED
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`define OR1200_DU_TB_IMPLEMENTED
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`endif
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`endif
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//
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// Address offsets of DU registers inside DU group
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// Address offsets of DU registers inside DU group
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`define OR1200_DU_OFS_DMR1 11'd16
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//
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`define OR1200_DU_OFS_DMR2 11'd17
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// To not implement a register, do not define its address
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`define OR1200_DU_OFS_DSR 11'd20
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//
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`define OR1200_DU_OFS_DRR 11'd21
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`ifdef OR1200_DU_HWBKPTS
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`define OR1200_DU_OFS_TBADR 11'h0ff
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`define OR1200_DU_DVR0 11'd0
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`define OR1200_DU_OFS_TBIA 11'h1xx
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`define OR1200_DU_DVR1 11'd1
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`define OR1200_DU_OFS_TBIM 11'h2xx
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`define OR1200_DU_DVR2 11'd2
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`define OR1200_DU_OFS_TBAR 11'h3xx
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`define OR1200_DU_DVR3 11'd3
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`define OR1200_DU_OFS_TBTS 11'h4xx
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`define OR1200_DU_DVR4 11'd4
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`define OR1200_DU_DVR5 11'd5
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`define OR1200_DU_DVR6 11'd6
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`define OR1200_DU_DVR7 11'd7
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`define OR1200_DU_DCR0 11'd8
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`define OR1200_DU_DCR1 11'd9
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`define OR1200_DU_DCR2 11'd10
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`define OR1200_DU_DCR3 11'd11
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`define OR1200_DU_DCR4 11'd12
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`define OR1200_DU_DCR5 11'd13
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`define OR1200_DU_DCR6 11'd14
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`define OR1200_DU_DCR7 11'd15
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`endif
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`define OR1200_DU_DMR1 11'd16
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`ifdef OR1200_DU_HWBKPTS
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`define OR1200_DU_DMR2 11'd17
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`define OR1200_DU_DWCR0 11'd18
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`define OR1200_DU_DWCR1 11'd19
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`endif
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`define OR1200_DU_DSR 11'd20
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`define OR1200_DU_DRR 11'd21
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`ifdef OR1200_DU_TB_IMPLEMENTED
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`define OR1200_DU_TBADR 11'h0ff
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`define OR1200_DU_TBIA 11'h1xx
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`define OR1200_DU_TBIM 11'h2xx
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`define OR1200_DU_TBAR 11'h3xx
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`define OR1200_DU_TBTS 11'h4xx
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`endif
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// Position of offset bits inside SPR address
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// Position of offset bits inside SPR address
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`define OR1200_DUOFS_BITS 10:0
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`define OR1200_DUOFS_BITS 10:0
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// Define if you want these DU registers to be implemented
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// DCR bits
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`define OR1200_DU_DMR1
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`define OR1200_DU_DCR_DP 0
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`define OR1200_DU_DMR2
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`define OR1200_DU_DCR_CC 3:1
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`define OR1200_DU_DSR
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`define OR1200_DU_DCR_SC 4
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`define OR1200_DU_DRR
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`define OR1200_DU_DCR_CT 7:5
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// DMR1 bits
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// DMR1 bits
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`define OR1200_DU_DMR1_CW0 1:0
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`define OR1200_DU_DMR1_CW1 3:2
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`define OR1200_DU_DMR1_CW2 5:4
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`define OR1200_DU_DMR1_CW3 7:6
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`define OR1200_DU_DMR1_CW4 9:8
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`define OR1200_DU_DMR1_CW5 11:10
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`define OR1200_DU_DMR1_CW6 13:12
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`define OR1200_DU_DMR1_CW7 15:14
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`define OR1200_DU_DMR1_CW8 17:16
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`define OR1200_DU_DMR1_CW9 19:18
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`define OR1200_DU_DMR1_CW10 21:20
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`define OR1200_DU_DMR1_ST 22
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`define OR1200_DU_DMR1_ST 22
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`define OR1200_DU_DMR1_BT 23
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`define OR1200_DU_DMR1_DXFW 24
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`define OR1200_DU_DMR1_ETE 25
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// DMR2 bits
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`define OR1200_DU_DMR2_WCE0 0
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`define OR1200_DU_DMR2_WCE1 1
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`define OR1200_DU_DMR2_AWTC 12:2
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`define OR1200_DU_DMR2_WGB 23:13
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// DWCR bits
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`define OR1200_DU_DWCR_COUNT 15:0
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`define OR1200_DU_DWCR_MATCH 31:16
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// DSR bits
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// DSR bits
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`define OR1200_DU_DSR_WIDTH 14
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`define OR1200_DU_DSR_WIDTH 14
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`define OR1200_DU_DSR_RSTE 0
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`define OR1200_DU_DSR_RSTE 0
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`define OR1200_DU_DSR_BUSEE 1
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`define OR1200_DU_DSR_BUSEE 1
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Line 1456... |
`define OR1200_VR_RES1_BITS 15:6
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`define OR1200_VR_RES1_BITS 15:6
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`define OR1200_VR_CFG_BITS 23:16
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`define OR1200_VR_CFG_BITS 23:16
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`define OR1200_VR_VER_BITS 31:24
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`define OR1200_VR_VER_BITS 31:24
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// VR values
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// VR values
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`define OR1200_VR_REV 6'h00
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`define OR1200_VR_REV 6'h01
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`define OR1200_VR_RES1 10'h000
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`define OR1200_VR_RES1 10'h000
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`define OR1200_VR_CFG 8'h00
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`define OR1200_VR_CFG 8'h00
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`define OR1200_VR_VER 8'h12
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`define OR1200_VR_VER 8'h12
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// UPR fields
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// UPR fields
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Line 1691... |
`define OR1200_DCFGR_NDP_BITS 2:0
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`define OR1200_DCFGR_NDP_BITS 2:0
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`define OR1200_DCFGR_WPCI_BITS 3
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`define OR1200_DCFGR_WPCI_BITS 3
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`define OR1200_DCFGR_RES1_BITS 31:4
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`define OR1200_DCFGR_RES1_BITS 31:4
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// DCFGR values
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// DCFGR values
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`ifdef OR1200_DU_HWBKPTS
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`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
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`ifdef OR1200_DU_DWCR0
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`define OR1200_DCFGR_WPCI 1'b1
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`else
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`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
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`endif
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`else
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`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
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`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
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`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
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`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
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`endif
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`define OR1200_DCFGR_RES1 28'h0000000
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`define OR1200_DCFGR_RES1 28'h0000000
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No newline at end of file
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No newline at end of file
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