| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/01/19 14:10:22 lampret
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// Fixed OR1200_XILINX_RAM32X1D.
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//
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.4 2002/01/14 09:44:12 lampret
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// Revision 1.4 2002/01/14 09:44:12 lampret
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// Default ASIC configuration does not sample WB inputs.
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// Default ASIC configuration does not sample WB inputs.
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| Line 177... |
Line 180... |
//`define OR1200_REGISTERED_INPUTS
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//`define OR1200_REGISTERED_INPUTS
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//
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//
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// Select between ASIC optimized and generic multiplier
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// Select between ASIC optimized and generic multiplier
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//
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//
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`define OR1200_ASIC_MULTP2_32X32
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//`define OR1200_ASIC_MULTP2_32X32
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//`define OR1200_GENERIC_MULTP2_32X32
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`define OR1200_GENERIC_MULTP2_32X32
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//
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//
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// Size/type of insn/data cache if implemented
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// Size/type of insn/data cache if implemented
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//
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//
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// `define OR1200_IC_1W_4KB
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// `define OR1200_IC_1W_4KB
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Line 312... |
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//
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//
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// ALUOPs
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// ALUOPs
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//
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//
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`define OR1200_ALUOP_WIDTH 4
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`define OR1200_ALUOP_WIDTH 4
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`define OR1200_ALUOP_NOP 4'd0
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`define OR1200_ALUOP_NOP 4'd4
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/* Order defined by arith insns that have two source operands both in regs
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/* Order defined by arith insns that have two source operands both in regs
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(see binutils/include/opcode/or32.h) */
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(see binutils/include/opcode/or32.h) */
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`define OR1200_ALUOP_ADD 4'd0
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`define OR1200_ALUOP_ADD 4'd0
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`define OR1200_ALUOP_ADDC 4'd1
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`define OR1200_ALUOP_ADDC 4'd1
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`define OR1200_ALUOP_SUB 4'd2
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`define OR1200_ALUOP_SUB 4'd2
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Line 1071... |
//
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//
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// 3 for 8 bytes, 4 for 16 bytes etc
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// 3 for 8 bytes, 4 for 16 bytes etc
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`define OR1200_DCLS 4
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`define OR1200_DCLS 4
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// Define to perform store refill (potential performance penalty)
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// `define OR1200_DC_STORE_REFILL
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//
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//
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// DC configurations
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// DC configurations
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//
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//
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`ifdef OR1200_DC_1W_4KB
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`ifdef OR1200_DC_1W_4KB
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`define OR1200_DCSIZE 12 // 4096
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`define OR1200_DCSIZE 12 // 4096
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