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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 788 and 790

Rev 788	Rev 790
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`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.13 2002/03/29 15:16:55 lampret`
	`// Some of the warnings fixed.`
	`//`
`// Revision 1.12 2002/03/28 19:25:42 lampret`	`// Revision 1.12 2002/03/28 19:25:42 lampret`
`// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.`	`// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.`
`//`	`//`
`// Revision 1.11 2002/03/28 19:13:17 lampret`	`// Revision 1.11 2002/03/28 19:13:17 lampret`
`// Updated defines.`	`// Updated defines.`
Line 281...	Line 284...
`// Do not change below unless you know what you are doing`	`// Do not change below unless you know what you are doing`
`//`	`//`

`//`	`//`
`// Enable additional synthesis directives if using`	`// Enable additional synthesis directives if using`
`// Synopsys synthesis tool`	`// _Synopsys_ synthesis tool`
`//`	`//`
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES	//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES

`//`	`//`
`// Operand width / register file address width`	`// Operand width / register file address width`