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https://opencores.org/ocsvn/or1k/or1k/trunk
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Rev 984 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.19 2002/08/18 19:53:08 lampret
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// Added store buffer.
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//
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// Revision 1.18 2002/08/15 06:04:11 lampret
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// Revision 1.18 2002/08/15 06:04:11 lampret
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// Fixed Xilinx trace buffer address. REported by Taylor Su.
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// Fixed Xilinx trace buffer address. REported by Taylor Su.
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//
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//
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// Revision 1.17 2002/08/12 05:31:44 lampret
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// Revision 1.17 2002/08/12 05:31:44 lampret
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// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
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// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
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// ensure strict memory model. Right now this is necessary because
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// ensure strict memory model. Right now this is necessary because
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// we don't make destinction between cached and cache inhibited
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// we don't make destinction between cached and cache inhibited
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// address space, so we simply empty store buffer until loads
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// address space, so we simply empty store buffer until loads
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// can begin.
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// can begin.
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//
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//
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`define OR1200_SB_IMPLEMENTED
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// [SB hasn't been tested yet, so don't enable it just yet!]
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//
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//`define OR1200_SB_IMPLEMENTED
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//
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//
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// Enable additional synthesis directives if using
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// Enable additional synthesis directives if using
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// _Synopsys_ synthesis tool
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// _Synopsys_ synthesis tool
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//
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//
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