| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.2 2002/01/28 01:16:00 lampret
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// Revision 1.2 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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| Line 75... |
Line 78... |
clk, rst,
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clk, rst,
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// I/F for translation
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// I/F for translation
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tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
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tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
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`ifdef OR1200_BIST
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// RAM BIST
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scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
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`endif
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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| Line 105... |
Line 113... |
output ure;
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output ure;
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output swe;
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output swe;
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output sre;
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output sre;
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output ci;
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output ci;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input scanb_rst,
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scanb_si,
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scanb_en,
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scanb_clk;
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output scanb_so;
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`endif
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//
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//
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// SPR access
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// SPR access
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//
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//
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input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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| Line 128... |
Line 147... |
wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
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wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
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wire tlb_tr_en;
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wire tlb_tr_en;
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wire tlb_tr_we;
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wire tlb_tr_we;
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wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
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wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
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wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
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wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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wire scanb_mr_so;
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wire scanb_tr_so;
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wire scanb_mr_si = scanb_si;
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wire scanb_tr_si = scanb_mr_so;
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assign scanb_so = scanb_tr_so;
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`endif
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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// dtlbwYmrX: vpn 31-19 v 0
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// dtlbwYmrX: vpn 31-19 v 0
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| Line 213... |
Line 242... |
// Instantiation of DTLB Match Registers
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// Instantiation of DTLB Match Registers
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//
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//
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or1200_spram_64x14 dtlb_mr_ram(
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or1200_spram_64x14 dtlb_mr_ram(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_mr_si),
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.scanb_so(scanb_mr_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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.ce(tlb_mr_en),
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.ce(tlb_mr_en),
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.we(tlb_mr_we),
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.we(tlb_mr_we),
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.oe(1'b1),
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.oe(1'b1),
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.addr(tlb_index),
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.addr(tlb_index),
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.di(tlb_mr_ram_in),
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.di(tlb_mr_ram_in),
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| Line 227... |
Line 264... |
// Instantiation of DTLB Translate Registers
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// Instantiation of DTLB Translate Registers
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//
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//
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or1200_spram_64x24 dtlb_tr_ram(
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or1200_spram_64x24 dtlb_tr_ram(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_tr_si),
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.scanb_so(scanb_tr_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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.ce(tlb_tr_en),
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.ce(tlb_tr_en),
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.we(tlb_tr_we),
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.we(tlb_tr_we),
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.oe(1'b1),
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.oe(1'b1),
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.addr(tlb_index),
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.addr(tlb_index),
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.di(tlb_tr_ram_in),
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.di(tlb_tr_ram_in),
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