| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.7 2002/10/17 20:04:40 lampret
|
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
|
//
|
// Revision 1.6 2002/03/29 15:16:55 lampret
|
// Revision 1.6 2002/03/29 15:16:55 lampret
|
// Some of the warnings fixed.
|
// Some of the warnings fixed.
|
//
|
//
|
// Revision 1.5 2002/02/14 15:34:02 simons
|
// Revision 1.5 2002/02/14 15:34:02 simons
|
// Lapsus fixed.
|
// Lapsus fixed.
|
| Line 106... |
Line 109... |
// RAM BIST
|
// RAM BIST
|
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
|
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
|
`endif
|
`endif
|
|
|
// DC i/f
|
// DC i/f
|
dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cycstb_o, dcdmmu_ci_o
|
qmemdmmu_err_i, qmemdmmu_tag_i, qmemdmmu_adr_o, qmemdmmu_cycstb_o, qmemdmmu_ci_o
|
);
|
);
|
|
|
parameter dw = `OR1200_OPERAND_WIDTH;
|
parameter dw = `OR1200_OPERAND_WIDTH;
|
parameter aw = `OR1200_OPERAND_WIDTH;
|
parameter aw = `OR1200_OPERAND_WIDTH;
|
|
|
| Line 157... |
Line 160... |
`endif
|
`endif
|
|
|
//
|
//
|
// DC I/F
|
// DC I/F
|
//
|
//
|
input dcdmmu_err_i;
|
input qmemdmmu_err_i;
|
input [3:0] dcdmmu_tag_i;
|
input [3:0] qmemdmmu_tag_i;
|
output [aw-1:0] dcdmmu_adr_o;
|
output [aw-1:0] qmemdmmu_adr_o;
|
output dcdmmu_cycstb_o;
|
output qmemdmmu_cycstb_o;
|
output dcdmmu_ci_o;
|
output qmemdmmu_ci_o;
|
|
|
//
|
//
|
// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
wire dtlb_spr_access;
|
wire dtlb_spr_access;
|
| Line 203... |
Line 206... |
|
|
//
|
//
|
// Put all outputs in inactive state
|
// Put all outputs in inactive state
|
//
|
//
|
assign spr_dat_o = 32'h00000000;
|
assign spr_dat_o = 32'h00000000;
|
assign dcdmmu_adr_o = dcpu_adr_i;
|
assign qmemdmmu_adr_o = dcpu_adr_i;
|
assign dcpu_tag_o = dcdmmu_tag_i;
|
assign dcpu_tag_o = qmemdmmu_tag_i;
|
assign dcdmmu_cycstb_o = dcpu_cycstb_i;
|
assign qmemdmmu_cycstb_o = dcpu_cycstb_i;
|
assign dcpu_err_o = dcdmmu_err_i;
|
assign dcpu_err_o = qmemdmmu_err_i;
|
assign dcdmmu_ci_o = `OR1200_DMMU_CI;
|
assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
assign scanb_so = scanb_si;
|
assign scanb_so = scanb_si;
|
`endif
|
`endif
|
|
|
`else
|
`else
|
| Line 231... |
Line 234... |
// Tags:
|
// Tags:
|
//
|
//
|
// OR1200_DTAG_TE - TLB miss Exception
|
// OR1200_DTAG_TE - TLB miss Exception
|
// OR1200_DTAG_PE - Page fault Exception
|
// OR1200_DTAG_PE - Page fault Exception
|
//
|
//
|
assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : dcdmmu_tag_i;
|
assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemdmmu_tag_i;
|
|
|
//
|
//
|
// dcpu_err_o
|
// dcpu_err_o
|
//
|
//
|
assign dcpu_err_o = miss | fault | dcdmmu_err_i;
|
assign dcpu_err_o = miss | fault | qmemdmmu_err_i;
|
|
|
//
|
//
|
// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.
|
// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
| Line 252... |
Line 255... |
dtlb_done <= #1 1'b0;
|
dtlb_done <= #1 1'b0;
|
|
|
//
|
//
|
// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.
|
// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.
|
//
|
//
|
assign dcdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;
|
assign qmemdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;
|
//assign dcdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
|
//assign qmemdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
|
|
|
//
|
//
|
// Cache Inhibit
|
// Cache Inhibit
|
//
|
//
|
assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
|
assign qmemdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
|
|
|
//
|
//
|
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
|
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
|
// one clock cycle after offset part.
|
// one clock cycle after offset part.
|
//
|
//
|
| Line 274... |
Line 277... |
|
|
//
|
//
|
// Physical address is either translated virtual address or
|
// Physical address is either translated virtual address or
|
// simply equal when DMMU is disabled
|
// simply equal when DMMU is disabled
|
//
|
//
|
// assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
|
// assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
|
assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
|
assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
|
|
|
//
|
//
|
// Output to SPRS unit
|
// Output to SPRS unit
|
//
|
//
|
assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
|
assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
|
