| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/01/22 03:23:47 lampret
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// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
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//
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// Revision 1.8 2002/09/08 19:31:52 lampret
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// Revision 1.8 2002/09/08 19:31:52 lampret
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// Fixed a typo, reported by Taylor Su.
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// Fixed a typo, reported by Taylor Su.
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//
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//
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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| Line 109... |
Line 112... |
du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
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du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
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du_read, du_write, du_except,
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du_read, du_write, du_except,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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// External Debug Interface
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// External Debug Interface
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
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dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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| Line 151... |
Line 154... |
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//
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//
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// External Debug Interface
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// External Debug Interface
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//
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//
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input dbg_stall_i; // External Stall Input
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input dbg_stall_i; // External Stall Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [2:0] dbg_op_i; // External Operation Select Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output dbg_bp_o; // Breakpoint Output
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output dbg_bp_o; // Breakpoint Output
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input dbg_stb_i; // External Address/Data Strobe
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input dbg_we_i; // External Write Enable
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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output [dw-1:0] dbg_dat_o; // External Data Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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output dbg_ack_i; // External Data Acknowledge (not WB compatible)
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//
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//
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// Some connections go directly from the CPU through DU to Debug I/F
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// Some connections go directly from the CPU through DU to Debug I/F
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//
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//
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| Line 194... |
Line 199... |
// Some connections go directly from Debug I/F through DU to the CPU
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// Some connections go directly from Debug I/F through DU to the CPU
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//
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//
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assign du_stall = dbg_stall_i;
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assign du_stall = dbg_stall_i;
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assign du_addr = dbg_adr_i;
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assign du_addr = dbg_adr_i;
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assign du_dat_o = dbg_dat_i;
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assign du_dat_o = dbg_dat_i;
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assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
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assign du_read = dbg_stb_i && !dbg_we_i;
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assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
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assign du_write = dbg_stb_i && dbg_we_i;
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//
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// Generate acknowledge -- just delay stb signal
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//
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reg dbg_ack_o;
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always @(posedge clk or posedge rst)
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if (rst)
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dbg_ack_o <= #1 1'b0;
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else
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dbg_ack_o <= #1 dbg_stb_i;
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`ifdef OR1200_DU_IMPLEMENTED
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`ifdef OR1200_DU_IMPLEMENTED
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//
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//
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// Debug Mode Register 1 (only ST and BT implemented)
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// Debug Mode Register 1 (only ST and BT implemented)
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