| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9.4.1 2004/01/15 06:46:38 markom
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// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.9 2003/01/22 03:23:47 lampret
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// Revision 1.9 2003/01/22 03:23:47 lampret
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// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
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// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
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//
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//
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// Revision 1.8 2002/09/08 19:31:52 lampret
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// Revision 1.8 2002/09/08 19:31:52 lampret
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// Fixed a typo, reported by Taylor Su.
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// Fixed a typo, reported by Taylor Su.
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| Line 164... |
Line 167... |
input dbg_stb_i; // External Address/Data Strobe
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input dbg_stb_i; // External Address/Data Strobe
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input dbg_we_i; // External Write Enable
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input dbg_we_i; // External Write Enable
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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output [dw-1:0] dbg_dat_o; // External Data Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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output dbg_ack_i; // External Data Acknowledge (not WB compatible)
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output dbg_ack_o; // External Data Acknowledge (not WB compatible)
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//
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//
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// Some connections go directly from the CPU through DU to Debug I/F
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// Some connections go directly from the CPU through DU to Debug I/F
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//
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//
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