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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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//
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//
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// Revision 1.14 2001/11/23 08:38:51 lampret
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// Revision 1.14 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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// Changed DSR/DRR behavior and exception detection.
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| Line 107... |
Line 110... |
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,
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sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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except_started, except_stop,
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except_started, except_stop,
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wb_pc, ex_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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esr, sr, lsu_addr
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esr, sr, lsu_addr
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);
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);
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//
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//
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// I/O
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// I/O
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| Line 155... |
Line 158... |
output except_start;
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output except_start;
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output except_started;
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output except_started;
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output [12:0] except_stop;
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output [12:0] except_stop;
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output [31:0] wb_pc;
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output [31:0] wb_pc;
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output [31:0] ex_pc;
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output [31:0] ex_pc;
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output [31:0] id_pc;
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//
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//
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// Internal regs and wires
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// Internal regs and wires
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//
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//
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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| Line 186... |
Line 190... |
//
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//
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// Simple combinatorial logic
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// Simple combinatorial logic
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//
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//
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assign except_started = extend_flush & except_start;
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assign except_started = extend_flush & except_start;
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assign lr_sav = ex_pc[31:2];
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assign lr_sav = ex_pc[31:2];
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assign except_start = (except_type != `OR1200_EXCEPT_NONE);
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
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assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
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//
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//
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// Order defines exception detection priority
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// Order defines exception detection priority
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//
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//
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| Line 205... |
Line 210... |
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE]
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE]
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};
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};
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assign except_stop = {
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assign except_stop = {
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inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
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inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
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ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
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| Line 220... |
Line 225... |
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
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ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_trap & du_dsr[`OR1200_DU_DSR_TE],
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sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_range & du_dsr[`OR1200_DU_DSR_RE]
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sig_range & du_dsr[`OR1200_DU_DSR_RE]
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};
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};
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//
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//
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// PC and Exception flags pipelines
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// PC and Exception flags pipelines
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| Line 232... |
Line 237... |
always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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id_pc <= #1 32'd0;
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id_pc <= #1 32'd0;
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id_exceptflags <= #1 4'b0000;
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id_exceptflags <= #1 4'b0000;
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end
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end
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else if (flushpipe) begin
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id_pc <= #1 32'h0000_0000;
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id_exceptflags <= #1 4'b0000;
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end
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else if (!id_freeze) begin
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else if (!id_freeze) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: id_pc <= %h", $time, if_pc);
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// synopsys translate_on
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`endif
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id_pc <= #1 if_pc;
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id_pc <= #1 if_pc;
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id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
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id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
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end
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end
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end
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end
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| Line 270... |
Line 274... |
ex_pc <= #1 32'd0;
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ex_pc <= #1 32'd0;
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ex_exceptflags <= #1 4'b0000;
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ex_exceptflags <= #1 4'b0000;
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delayed1_ex_dslot <= #1 1'b0;
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delayed1_ex_dslot <= #1 1'b0;
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delayed2_ex_dslot <= #1 1'b0;
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delayed2_ex_dslot <= #1 1'b0;
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end
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end
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else if (flushpipe) begin
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ex_dslot <= #1 1'b0;
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ex_pc <= #1 32'h0000_0000;
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ex_exceptflags <= #1 4'b0000;
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delayed1_ex_dslot <= #1 1'b0;
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delayed2_ex_dslot <= #1 1'b0;
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end
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else if (!ex_freeze & id_freeze) begin
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else if (!ex_freeze & id_freeze) begin
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ex_dslot <= #1 1'b0;
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ex_dslot <= #1 1'b0;
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ex_pc <= #1 id_pc;
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ex_pc <= #1 id_pc;
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ex_exceptflags <= #1 4'b0000;
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ex_exceptflags <= #1 4'b0000;
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delayed1_ex_dslot <= #1 ex_dslot;
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delayed1_ex_dslot <= #1 ex_dslot;
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| Line 306... |
Line 317... |
end
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end
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//
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//
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// Flush pipeline
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// Flush pipeline
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//
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//
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assign flushpipe = except_flushpipe | pc_we | extend_flush | extend_flush_last;
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assign flushpipe = except_flushpipe | pc_we | extend_flush;
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//
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//
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// We have started execution of exception handler:
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// We have started execution of exception handler:
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// 1. Asserted for 3 clock cycles
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// 1. Asserted for 3 clock cycles
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// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
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// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
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//
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//
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assign except_flushpipe = |except_trig;
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assign except_flushpipe = |except_trig & !state;
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//
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//
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// Exception FSM that sequences execution of exception handler
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// Exception FSM that sequences execution of exception handler
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//
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//
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// except_type signals which exception handler we start fetching in:
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// except_type signals which exception handler we start fetching in:
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| Line 409... |
Line 420... |
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_0001_xxxx: begin
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13'b0_0000_0001_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_0000_1xxx: begin
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13'b0_0000_0000_1xxx: begin
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except_type <= #1 `OR1200_EXCEPT_LPINT;
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except_type <= #1 `OR1200_EXCEPT_LPINT;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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| Line 444... |
Line 455... |
eear <= #1 datain;
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eear <= #1 datain;
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if (esr_we)
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if (esr_we)
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esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
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esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
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end
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end
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`OR1200_EXCEPTFSM_FLU1:
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`OR1200_EXCEPTFSM_FLU1:
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if (!if_stall & !id_freeze)
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// if (!if_stall & !id_freeze)
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state <= #1 `OR1200_EXCEPTFSM_FLU2;
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state <= #1 `OR1200_EXCEPTFSM_FLU2;
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`OR1200_EXCEPTFSM_FLU2:
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`OR1200_EXCEPTFSM_FLU2:
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if (except_type == `OR1200_EXCEPT_TRAP) begin
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if (except_type == `OR1200_EXCEPT_TRAP) begin
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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extend_flush <= #1 1'b0;
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extend_flush <= #1 1'b0;
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extend_flush_last <= #1 1'b0;
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extend_flush_last <= #1 1'b0;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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end
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end
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else if (!if_stall & !id_freeze)
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else
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// if (!if_stall & !id_freeze)
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state <= #1 `OR1200_EXCEPTFSM_FLU3;
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state <= #1 `OR1200_EXCEPTFSM_FLU3;
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`OR1200_EXCEPTFSM_FLU3:
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`OR1200_EXCEPTFSM_FLU3:
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if (!if_stall && !id_freeze)
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// if (!if_stall && !id_freeze)
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begin
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begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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if (except_flushpipe)
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if (except_flushpipe)
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$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);
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$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);
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| Line 469... |
Line 481... |
state <= #1 `OR1200_EXCEPTFSM_FLU4;
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state <= #1 `OR1200_EXCEPTFSM_FLU4;
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end
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end
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`OR1200_EXCEPTFSM_FLU4: begin
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`OR1200_EXCEPTFSM_FLU4: begin
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state <= #1 `OR1200_EXCEPTFSM_FLU5;
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state <= #1 `OR1200_EXCEPTFSM_FLU5;
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extend_flush <= #1 1'b0;
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extend_flush <= #1 1'b0;
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extend_flush_last <= #1 1'b1;
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extend_flush_last <= #1 1'b0; // damjan
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end
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end
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`OR1200_EXCEPTFSM_FLU5: begin
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`OR1200_EXCEPTFSM_FLU5: begin
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if (!if_stall && !id_freeze) begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display(" INFO: Just finished flushing pipeline.");
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$display(" INFO: Just finished flushing pipeline.");
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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extend_flush_last <= #1 1'b0;
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extend_flush_last <= #1 1'b0;
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end
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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