| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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| Line 209... |
Line 212... |
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE]
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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};
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};
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assign except_stop = {
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assign except_stop = {
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inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
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inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
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ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IPFE],
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| Line 224... |
Line 227... |
sig_align & du_dsr[`OR1200_DU_DSR_AE],
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sig_align & du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
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ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_range & du_dsr[`OR1200_DU_DSR_RE],
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sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_range & du_dsr[`OR1200_DU_DSR_RE]
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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};
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};
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//
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//
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// PC and Exception flags pipelines
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// PC and Exception flags pipelines
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//
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//
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