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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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//
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// Revision 1.6 2002/01/18 14:21:43 lampret
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// Revision 1.6 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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// Fixed 'the NPC single-step fix'.
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//
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//
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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| Line 126... |
Line 129... |
sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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except_started, except_stop, ex_void,
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except_started, except_stop, ex_void,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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esr, sr, lsu_addr
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esr, sr, lsu_addr, abort_ex
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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| Line 174... |
Line 177... |
output except_started;
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output except_started;
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output [12:0] except_stop;
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output [12:0] except_stop;
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input ex_void;
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input ex_void;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_npc;
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output [31:0] spr_dat_npc;
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output abort_ex;
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//
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//
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// Internal regs and wires
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// Internal regs and wires
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//
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//
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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| Line 211... |
Line 215... |
assign spr_dat_ppc = wb_pc;
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux. except_test fails
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//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux, except_tets almost works (priority fails)
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assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions
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//
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//
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// Order defines exception detection priority
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// Order defines exception detection priority
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//
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//
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assign except_trig = {
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assign except_trig = {
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tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
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int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
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int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
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sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
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sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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};
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};
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assign except_stop = {
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assign except_stop = {
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tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
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int_pending & du_dsr[`OR1200_DU_DSR_IE],
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int_pending & du_dsr[`OR1200_DU_DSR_IE],
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ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
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ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
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sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
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sig_align & du_dsr[`OR1200_DU_DSR_AE],
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sig_align & du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
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sig_range & du_dsr[`OR1200_DU_DSR_RE],
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sig_range & du_dsr[`OR1200_DU_DSR_RE],
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sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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};
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};
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| Line 415... |
Line 421... |
end
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end
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esr <= #1 sr;
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esr <= #1 sr;
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casex (except_trig)
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casex (except_trig)
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13'b1_xxxx_xxxx_xxxx: begin
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13'b1_xxxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_INT;
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except_type <= #1 `OR1200_EXCEPT_TICK;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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13'b0_1xxx_xxxx_xxxx: begin
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13'b0_1xxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
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except_type <= #1 `OR1200_EXCEPT_INT;
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eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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13'b0_01xx_xxxx_xxxx: begin
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13'b0_01xx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_IPF;
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except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
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eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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13'b0_001x_xxxx_xxxx: begin
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13'b0_001x_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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except_type <= #1 `OR1200_EXCEPT_IPF;
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eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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13'b0_0001_xxxx_xxxx: begin
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13'b0_0001_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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eear <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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13'b0_0000_1xxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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eear <= #1 ex_pc;
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eear <= #1 ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_1xxx_xxxx: begin
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13'b0_0000_01xx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_01xx_xxxx: begin
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13'b0_0000_001x_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
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except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_001x_xxxx: begin
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13'b0_0000_0001_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_DPF;
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except_type <= #1 `OR1200_EXCEPT_DPF;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_0001_xxxx: begin
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13'b0_0000_0000_1xxx: begin // Data Bus Error
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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except_type <= #1 `OR1200_EXCEPT_BUSERR;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_0000_1xxx: begin
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except_type <= #1 `OR1200_EXCEPT_TICK;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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13'b0_0000_0000_01xx: begin
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13'b0_0000_0000_01xx: begin
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except_type <= #1 `OR1200_EXCEPT_RANGE;
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except_type <= #1 `OR1200_EXCEPT_RANGE;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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13'b0_0000_0000_001x: begin
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13'b0_0000_0000_001x: begin
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except_type <= #1 `OR1200_EXCEPT_TRAP;
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except_type <= #1 `OR1200_EXCEPT_TRAP;
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eear <= #1 32'h0000_0000;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_0000_0001: begin
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13'b0_0000_0000_0001: begin
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except_type <= #1 `OR1200_EXCEPT_SYSCALL;
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except_type <= #1 `OR1200_EXCEPT_SYSCALL;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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