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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_freeze.v] - Diff between revs 1163 and 1171

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Rev 1163	Rev 1171
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2002/07/31 02:04:35 lampret`
	`// MAC now follows software convention (signed multiply instead of unsigned).`
	`//`
`// Revision 1.5 2002/07/14 22:17:17 lampret`	`// Revision 1.5 2002/07/14 22:17:17 lampret`
`// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.`	`// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.`
`//`	`//`
`// Revision 1.4 2002/03/29 15:16:55 lampret`	`// Revision 1.4 2002/03/29 15:16:55 lampret`
`// Some of the warnings fixed.`	`// Some of the warnings fixed.`
Line 181...	Line 184...
`//`	`//`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`multicycle_cnt <= #1 3'b0;`	`multicycle_cnt <= #1 3'b0;`
`else if (multicycle_cnt)`	`else if (multicycle_cnt)`
`multicycle_cnt <= #1 multicycle_cnt - 'd1;`	`multicycle_cnt <= #1 multicycle_cnt - 1'd1;`
`else if (multicycle & !ex_freeze)`	`else if (multicycle & !ex_freeze)`
`multicycle_cnt <= #1 multicycle;`	`multicycle_cnt <= #1 multicycle;`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_freeze.v] - Diff between revs 1163 and 1171