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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_freeze.v] - Diff between revs 617 and 788

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Rev 617	Rev 788
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2002/01/28 01:16:00 lampret`
	`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
	`//`
`// Revision 1.2 2002/01/14 06:18:22 lampret`	`// Revision 1.2 2002/01/14 06:18:22 lampret`
`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`	`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
`//`	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
Line 121...	Line 124...

`//`	`//`
`// Internal wires and regs`	`// Internal wires and regs`
`//`	`//`
`wire multicycle_freeze;`	`wire multicycle_freeze;`
`reg [2:0] multicycle_cnt;`	reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;

`//`	`//`
`// Pipeline freeze`	`// Pipeline freeze`
`//`	`//`
`// Rules how to create freeze signals:`	`// Rules how to create freeze signals:`

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_freeze.v] - Diff between revs 617 and 788