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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.7 2003/04/20 22:23:57 lampret
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// Revision 1.7 2003/04/20 22:23:57 lampret
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// No functional change. Only added customization for exception vectors.
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// No functional change. Only added customization for exception vectors.
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//
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//
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// Revision 1.6 2002/03/29 15:16:55 lampret
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// Revision 1.6 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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| Line 103... |
Line 106... |
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// Internal i/f
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// Internal i/f
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branch_op, except_type, except_prefix,
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branch_op, except_type, except_prefix,
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branch_addrofs, lr_restor, flag, taken, except_start,
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branch_addrofs, lr_restor, flag, taken, except_start,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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genpc_freeze, no_more_dslot
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genpc_freeze, genpc_stop_prefetch, no_more_dslot
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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| Line 142... |
Line 145... |
input [31:2] binsn_addr;
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input [31:2] binsn_addr;
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input [31:0] epcr;
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input [31:0] epcr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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input spr_pc_we;
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input spr_pc_we;
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input genpc_refetch;
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input genpc_refetch;
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input genpc_stop_prefetch;
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input genpc_freeze;
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input genpc_freeze;
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input no_more_dslot;
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input no_more_dslot;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [31:2] pcreg;
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reg [31:2] pcreg;
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reg [31:0] pc;
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reg [31:0] pc;
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reg taken; /* Set to in case of jump or taken branch */
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reg taken; /* Set to in case of jump or taken branch */
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reg genpc_refetch_r;
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//
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//
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// Address of insn to be fecthed
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// Address of insn to be fecthed
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//
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//
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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| Line 162... |
Line 167... |
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//
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//
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// Control access to IC subsystem
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// Control access to IC subsystem
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//
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//
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// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
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// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
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assign icpu_cycstb_o = !genpc_freeze;
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assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
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//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
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//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
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assign icpu_sel_o = 4'b1111;
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assign icpu_sel_o = 4'b1111;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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//
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//
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// genpc_freeze_r
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//
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always @(posedge clk or posedge rst)
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if (rst)
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genpc_refetch_r <= #1 1'b0;
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else if (genpc_refetch)
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genpc_refetch_r <= #1 1'b1;
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else
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genpc_refetch_r <= #1 1'b0;
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//
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// Async calculation of new PC value. This value is used for addressing the IC.
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// Async calculation of new PC value. This value is used for addressing the IC.
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//
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//
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always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
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always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
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or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
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or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
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casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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| Line 277... |
Line 295... |
// PC register
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// PC register
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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// pcreg <= #1 30'd63;
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// pcreg <= #1 30'd63;
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pcreg <= #1 ({`OR1200_EXCEPT_RESET, `OR1200_EXCEPT_VV} - 1) >> 2;
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pcreg <= #1 ({{4{except_prefix}}, `OR1200_EXCEPT_MMMM, `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_VV} - 1) >> 2;
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else if (spr_pc_we)
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else if (spr_pc_we)
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pcreg <= #1 spr_dat_i[31:2];
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pcreg <= #1 spr_dat_i[31:2];
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else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
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else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
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// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
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// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
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pcreg <= #1 pc[31:2];
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pcreg <= #1 pc[31:2];
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