| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.10 2001/11/20 18:46:15 simons
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// Revision 1.10 2001/11/20 18:46:15 simons
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// Break point bug fixed
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// Break point bug fixed
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| Line 83... |
Line 86... |
// External i/f to IC
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// External i/f to IC
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icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,
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icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,
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icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
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icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
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// Internal i/f
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// Internal i/f
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branch_op, except_type,
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branch_op, except_type, except_prefix,
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branch_addrofs, lr_restor, flag, taken, except_start,
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branch_addrofs, lr_restor, flag, taken, except_start,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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genpc_freeze, flushpipe
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genpc_freeze, flushpipe
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);
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);
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| Line 117... |
Line 120... |
//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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input except_prefix;
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input [31:2] branch_addrofs;
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input [31:2] branch_addrofs;
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input [31:0] lr_restor;
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input [31:0] lr_restor;
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input flag;
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input flag;
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output taken;
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output taken;
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input except_start;
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input except_start;
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| Line 156... |
Line 160... |
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//
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//
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// Async calculation of new PC value. This value is used for addressing the IC.
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// Async calculation of new PC value. This value is used for addressing the IC.
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//
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//
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always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
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always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
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or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i) begin
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or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
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casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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{2'b00, `OR1200_BRANCHOP_NOP}: begin
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{2'b00, `OR1200_BRANCHOP_NOP}: begin
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pc = {pcreg + 'd1, 2'b0};
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pc = {pcreg + 'd1, 2'b0};
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taken = 1'b0;
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taken = 1'b0;
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end
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end
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| Line 242... |
Line 246... |
`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("Starting exception: %h.", except_type);
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$display("Starting exception: %h.", except_type);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pc = { 20'h0_0000, except_type, 8'h00};
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pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};
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taken = 1'b1;
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taken = 1'b1;
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end
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end
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default: begin
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default: begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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