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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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Line 87... |
module or1200_genpc(
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module or1200_genpc(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// External i/f to IC
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// External i/f to IC
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icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
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icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
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// Internal i/f
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// Internal i/f
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branch_op, except_type, except_prefix,
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branch_op, except_type, except_prefix,
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branch_addrofs, lr_restor, flag, taken, except_start,
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branch_addrofs, lr_restor, flag, taken, except_start,
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Line 111... |
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//
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//
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// External i/f to IC
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// External i/f to IC
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//
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//
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output [31:0] icpu_adr_o;
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output [31:0] icpu_adr_o;
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output icpu_cyc_o;
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output icpu_cycstb_o;
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output icpu_stb_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_tag_o;
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output [3:0] icpu_tag_o;
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input icpu_ack_i;
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input icpu_ack_i;
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input icpu_rty_i;
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input icpu_rty_i;
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input icpu_err_i;
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input icpu_err_i;
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Line 157... |
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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//
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//
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// Control access to IC subsystem
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// Control access to IC subsystem
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//
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//
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// assign icpu_cyc_o = !genpc_freeze & !no_more_dslot;
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// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
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assign icpu_cyc_o = !genpc_freeze;
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assign icpu_cycstb_o = !genpc_freeze;
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assign icpu_stb_o = icpu_cyc_o;
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assign icpu_sel_o = 4'b1111;
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assign icpu_sel_o = 4'b1111;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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//
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//
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// Async calculation of new PC value. This value is used for addressing the IC.
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// Async calculation of new PC value. This value is used for addressing the IC.
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