OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_ic_fsm.v] - Diff between revs 788 and 1161

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 788 Rev 1161
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.7  2002/03/29 15:16:55  lampret
 
// Some of the warnings fixed.
 
//
// Revision 1.6  2002/03/28 19:10:40  lampret
// Revision 1.6  2002/03/28 19:10:40  lampret
// Optimized cache controller FSM.
// Optimized cache controller FSM.
//
//
// Revision 1.1.1.1  2002/03/21 16:55:45  lampret
// Revision 1.1.1.1  2002/03/21 16:55:45  lampret
// First import of the "new" XESS XSV environment.
// First import of the "new" XESS XSV environment.
Line 143... Line 146...
reg                             cache_inhibit;
reg                             cache_inhibit;
 
 
//
//
// Generate of ICRAM write enables
// Generate of ICRAM write enables
//
//
assign icram_we = {4{load & biudata_valid & !cache_inhibit}};
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
 
 
//
//
// BIU read and write
// BIU read and write
//
//

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.