| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
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// First import of the "new" XESS XSV environment.
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//
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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//
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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| Line 183... |
Line 190... |
hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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load <= #1 1'b1;
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load <= #1 1'b1;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else begin // idle
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else begin // idle
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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`OR1200_ICFSM_CFETCH: begin // fetch
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`OR1200_ICFSM_CFETCH: begin // fetch
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if (icimmu_cycstb_i & icimmu_ci_i)
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if (icimmu_cycstb_i & icimmu_ci_i)
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cache_inhibit <= #1 1'b1;
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cache_inhibit <= #1 1'b1;
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if (hitmiss_eval)
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if (hitmiss_eval)
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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if (!ic_en)
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if ((!ic_en) ||
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state <= #1 `OR1200_ICFSM_IDLE;
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(hitmiss_eval & !icimmu_cycstb_i) || // fetch aborted (usually caused by IMMU)
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else if (hitmiss_eval & !icimmu_cycstb_i) begin // fetch aborted (usually caused by IMMU)
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(biudata_error) || // fetch terminated with an error
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state <= #1 `OR1200_ICFSM_IDLE;
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(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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else if (biudata_error) begin // fetch terminated with an error
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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else if (cache_inhibit & biudata_valid) begin // fetch from cache-inhibited page
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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| Line 221... |
Line 216... |
hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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cnt <= #1 `OR1200_ICLS-2;
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cnt <= #1 `OR1200_ICLS-2;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (!tagcomp_miss & !icimmu_ci_i) begin // fetch hit, finish immediately
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else if (!tagcomp_miss & !icimmu_ci_i) begin // fetch hit, finish immediately
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state <= #1 `OR1200_ICFSM_CFETCH;
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saved_addr_r <= #1 start_addr;
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saved_addr_r <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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load <= #1 1'b1;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (!icimmu_cycstb_i) begin // fetch aborted (usually caused by exception)
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else if (!icimmu_cycstb_i) begin // fetch aborted (usually caused by exception)
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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| Line 237... |
Line 229... |
end
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end
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else // fetch in-progress
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else // fetch in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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end
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end
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`OR1200_ICFSM_LREFILL3 : begin
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`OR1200_ICFSM_LREFILL3 : begin
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if (!ic_en)
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if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
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state <= #1 `OR1200_ICFSM_IDLE;
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else if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
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cnt <= #1 cnt - 'd1;
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cnt <= #1 cnt - 'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
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end
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end
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else if (biudata_valid) begin // last fetch of line refill
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else if (biudata_valid) begin // last fetch of line refill
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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