URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_ic_tag.v] - Diff between revs 1063 and 1069

Rev 1063	Rev 1069
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/10/17 20:04:40 lampret`
	`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.8 2001/10/21 17:57:16 lampret`	`// Revision 1.8 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
Line 73...	Line 76...
`// Clock and reset`	`// Clock and reset`
`clk, rst,`	`clk, rst,`

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`scanb_rst, scanb_si, scanb_so, scanb_eni, scanb_clk,`	`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
`endif	`endif

`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, tag_v, tag`	`addr, en, we, datain, tag_v, tag`
`);`	`);`