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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_ic_tag.v] - Diff between revs 1163 and 1214

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Rev 1163	Rev 1214
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2002/10/24 22:19:04 mohor`
	`// Signal scanb_eni renamed to scanb_en`
	`//`
`// Revision 1.2 2002/10/17 20:04:40 lampret`	`// Revision 1.2 2002/10/17 20:04:40 lampret`
`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`	`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
`//`	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
Line 76...	Line 79...
`// Clock and reset`	`// Clock and reset`
`clk, rst,`	`clk, rst,`

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
`endif	`endif

`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, tag_v, tag`	`addr, en, we, datain, tag_v, tag`
`);`	`);`
Line 100...	Line 103...

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
`input scanb_rst,`	`input mbist_si_i;`
`scanb_si,`	input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
`scanb_en,`	`output mbist_so_o;`
`scanb_clk;`
`output scanb_so;`
`endif	`endif

`//`	`//`
`// Internal i/f`	`// Internal i/f`
`//`	`//`
Line 125...	Line 126...
`// Insn cache not implemented`	`// Insn cache not implemented`
`//`	`//`
`assign tag = {dw-1{1'b0}};`	`assign tag = {dw-1{1'b0}};`
`assign tag_v = 1'b0;`	`assign tag_v = 1'b0;`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`assign scanb_so = scanb_si;`	`assign mbist_so_o = mbist_si_i;`
`endif	`endif

`else	`else

`//`	`//`
Line 141...	Line 142...
`ifdef OR1200_IC_1W_8KB	`ifdef OR1200_IC_1W_8KB
`or1200_spram_512x20 ic_tag0(`	`or1200_spram_512x20 ic_tag0(`
`endif	`endif
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_si_i),`
`.scanb_si(scanb_si),`	`.mbist_so_o(mbist_so_o),`
`.scanb_so(scanb_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we),`	`.we(we),`

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_ic_tag.v] - Diff between revs 1163 and 1214