| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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| Line 92... |
Line 95... |
icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
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icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
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icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
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icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
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// Internal i/f
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// Internal i/f
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ic_en,
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ic_en,
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icimmu_adr_i, icimmu_cyc_i, icimmu_stb_i, icimmu_ci_i,
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icimmu_adr_i, icimmu_cycstb_i, icimmu_ci_i,
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icpu_we_i, icpu_sel_i, icpu_tag_i,
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icpu_we_i, icpu_sel_i, icpu_tag_i,
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icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o,
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icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o,
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// SPRs
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// SPRs
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spr_cs, spr_write, spr_dat_i
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spr_cs, spr_write, spr_dat_i
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| Line 131... |
Line 134... |
//
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//
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// Internal I/F
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// Internal I/F
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//
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//
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input ic_en;
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input ic_en;
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input [31:0] icimmu_adr_i;
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input [31:0] icimmu_adr_i;
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input icimmu_cyc_i;
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input icimmu_cycstb_i;
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input icimmu_stb_i;
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input icimmu_ci_i;
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input icimmu_ci_i;
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input icpu_we_i;
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input icpu_we_i;
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input [3:0] icpu_sel_i;
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input [3:0] icpu_sel_i;
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input [3:0] icpu_tag_i;
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input [3:0] icpu_tag_i;
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output [dw-1:0] icpu_dat_o;
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output [dw-1:0] icpu_dat_o;
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| Line 171... |
Line 173... |
wire ic_inv;
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wire ic_inv;
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wire icfsm_first_hit_ack;
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wire icfsm_first_hit_ack;
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wire icfsm_first_miss_ack;
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wire icfsm_first_miss_ack;
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wire icfsm_first_miss_err;
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wire icfsm_first_miss_err;
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wire icfsm_burst;
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wire icfsm_burst;
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wire icfsm_tag_we;
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//
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//
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// Simple assignments
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// Simple assignments
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//
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//
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assign icbiu_adr_o = ic_addr;
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assign icbiu_adr_o = ic_addr;
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assign ic_inv = spr_cs & spr_write;
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assign ic_inv = spr_cs & spr_write;
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assign ictag_we = (icfsm_biu_read & icbiu_ack_i) | ic_inv;
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assign ictag_we = icfsm_tag_we | ic_inv;
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assign ictag_addr = ic_inv ? spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] : ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
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assign ictag_addr = ic_inv ? spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] : ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
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assign ictag_en = ic_inv | ic_en;
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assign ictag_en = ic_inv | ic_en;
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assign ictag_v = ~ic_inv;
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assign ictag_v = ~ic_inv;
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//
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//
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| Line 191... |
Line 194... |
assign icbiu_dat_o = 32'h00000000;
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assign icbiu_dat_o = 32'h00000000;
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//
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//
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// Bypases of the IC when IC is disabled
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// Bypases of the IC when IC is disabled
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//
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//
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assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icimmu_cyc_i;
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assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i;
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assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icimmu_stb_i;
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assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i;
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assign icbiu_we_o = 1'b0;
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assign icbiu_we_o = 1'b0;
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assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icpu_sel_i;
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assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icpu_sel_i;
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assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
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assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
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assign icimmu_rty_o = ~icpu_ack_o & ~icimmu_err_o;
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assign icimmu_rty_o = ~icpu_ack_o & ~icimmu_err_o;
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assign icimmu_tag_o = icimmu_err_o ? `OR1200_ITAG_BE : icpu_tag_i;
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assign icimmu_tag_o = icimmu_err_o ? `OR1200_ITAG_BE : icpu_tag_i;
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| Line 237... |
Line 240... |
//
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//
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or1200_ic_fsm or1200_ic_fsm(
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or1200_ic_fsm or1200_ic_fsm(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.ic_en(ic_en),
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.ic_en(ic_en),
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.icimmu_cyc_i(icimmu_cyc_i),
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.icimmu_cycstb_i(icimmu_cycstb_i),
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.icimmu_stb_i(icimmu_stb_i),
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.icimmu_ci_i(icimmu_ci_i),
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.icimmu_ci_i(icimmu_ci_i),
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.icpu_sel_i(icpu_sel_i),
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.icpu_sel_i(icpu_sel_i),
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.tagcomp_miss(tagcomp_miss),
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.tagcomp_miss(tagcomp_miss),
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.biudata_valid(icbiu_ack_i),
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.biudata_valid(icbiu_ack_i),
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.biudata_error(icbiu_err_i),
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.biudata_error(icbiu_err_i),
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| Line 251... |
Line 253... |
.icram_we(icram_we),
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.icram_we(icram_we),
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.biu_read(icfsm_biu_read),
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.biu_read(icfsm_biu_read),
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.first_hit_ack(icfsm_first_hit_ack),
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.first_hit_ack(icfsm_first_hit_ack),
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.first_miss_ack(icfsm_first_miss_ack),
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.first_miss_ack(icfsm_first_miss_ack),
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.first_miss_err(icfsm_first_miss_err),
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.first_miss_err(icfsm_first_miss_err),
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.burst(icfsm_burst)
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.burst(icfsm_burst),
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.tag_we(icfsm_tag_we)
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);
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);
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//
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//
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// Instantiation of IC main memory
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// Instantiation of IC main memory
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//
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//
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