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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_ic_top.v] - Diff between revs 660 and 788

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Rev 660 Rev 788
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.5  2002/02/11 04:33:17  lampret
 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
 
//
// Revision 1.4  2002/02/01 19:56:54  lampret
// Revision 1.4  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
// Fixed combinational loops.
//
//
// Revision 1.3  2002/01/28 01:16:00  lampret
// Revision 1.3  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
Line 96... Line 99...
        icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
        icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
 
 
        // Internal i/f
        // Internal i/f
        ic_en,
        ic_en,
        icimmu_adr_i, icimmu_cycstb_i, icimmu_ci_i,
        icimmu_adr_i, icimmu_cycstb_i, icimmu_ci_i,
        icpu_we_i, icpu_sel_i, icpu_tag_i,
        icpu_sel_i, icpu_tag_i,
        icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o,
        icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o,
 
 
        // SPRs
        // SPRs
        spr_cs, spr_write, spr_dat_i
        spr_cs, spr_write, spr_dat_i
);
);
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//
//
input                           ic_en;
input                           ic_en;
input   [31:0]                   icimmu_adr_i;
input   [31:0]                   icimmu_adr_i;
input                           icimmu_cycstb_i;
input                           icimmu_cycstb_i;
input                           icimmu_ci_i;
input                           icimmu_ci_i;
input                           icpu_we_i;
 
input   [3:0]                    icpu_sel_i;
input   [3:0]                    icpu_sel_i;
input   [3:0]                    icpu_tag_i;
input   [3:0]                    icpu_tag_i;
output  [dw-1:0]         icpu_dat_o;
output  [dw-1:0]         icpu_dat_o;
output                          icpu_ack_o;
output                          icpu_ack_o;
output                          icimmu_rty_o;
output                          icimmu_rty_o;
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        .clk(clk),
        .clk(clk),
        .rst(rst),
        .rst(rst),
        .ic_en(ic_en),
        .ic_en(ic_en),
        .icimmu_cycstb_i(icimmu_cycstb_i),
        .icimmu_cycstb_i(icimmu_cycstb_i),
        .icimmu_ci_i(icimmu_ci_i),
        .icimmu_ci_i(icimmu_ci_i),
        .icpu_sel_i(icpu_sel_i),
 
        .tagcomp_miss(tagcomp_miss),
        .tagcomp_miss(tagcomp_miss),
        .biudata_valid(icbiu_ack_i),
        .biudata_valid(icbiu_ack_i),
        .biudata_error(icbiu_err_i),
        .biudata_error(icbiu_err_i),
        .start_addr(icimmu_adr_i),
        .start_addr(icimmu_adr_i),
        .saved_addr(saved_addr),
        .saved_addr(saved_addr),

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