| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.10 2002/09/16 03:08:56 lampret
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// Revision 1.10 2002/09/16 03:08:56 lampret
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// Disabled cache inhibit atttribute.
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// Disabled cache inhibit atttribute.
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//
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//
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// Revision 1.9 2002/08/18 19:54:17 lampret
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// Revision 1.9 2002/08/18 19:54:17 lampret
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// Added store buffer.
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// Added store buffer.
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| Line 193... |
Line 196... |
wire itlb_done;
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wire itlb_done;
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wire fault;
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wire fault;
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wire miss;
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wire miss;
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wire page_cross;
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wire page_cross;
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reg [31:0] icpu_adr_o;
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reg [31:0] icpu_adr_o;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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`ifdef OR1200_NO_IMMU
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`ifdef OR1200_NO_IMMU
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`else
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`else
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reg itlb_en_r;
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reg itlb_en_r;
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reg dis_spr_access;
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reg dis_spr_access;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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`endif
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`endif
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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| Line 226... |
Line 229... |
icpu_adr_o <= #1 icpu_adr_i;
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icpu_adr_o <= #1 icpu_adr_i;
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`else
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`else
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Unsupported !!!
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Unsupported !!!
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`endif
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`endif
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//
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// Page cross
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//
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// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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//
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assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
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//
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// one clock cycle after offset part.
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//
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always @(posedge clk or posedge rst)
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if (rst)
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icpu_vpn_r <= #1 {31-`OR1200_IMMU_PS{1'b0}};
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else
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icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS];
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`ifdef OR1200_NO_IMMU
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`ifdef OR1200_NO_IMMU
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//
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//
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// Put all outputs in inactive state
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// Put all outputs in inactive state
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//
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//
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assign spr_dat_o = 32'h00000000;
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assign spr_dat_o = 32'h00000000;
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assign icimmu_adr_o = icpu_adr_i;
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assign icimmu_adr_o = icpu_adr_i;
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assign icpu_tag_o = icimmu_tag_i;
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assign icpu_tag_o = icimmu_tag_i;
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assign icimmu_cycstb_o = icpu_cycstb_i;
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assign icimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
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assign icpu_rty_o = icimmu_rty_i;
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assign icpu_rty_o = icimmu_rty_i;
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assign icpu_err_o = icimmu_err_i;
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assign icpu_err_o = icimmu_err_i;
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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assign scanb_so = scanb_si;
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assign scanb_so = scanb_si;
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| Line 324... |
Line 344... |
// assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// However this causes a async combinational loop so we stick to
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// However this causes a async combinational loop so we stick to
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// no cache inhibit.
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// no cache inhibit.
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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//
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// Page cross
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//
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// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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//
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assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
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//
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// one clock cycle after offset part.
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//
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always @(posedge clk or posedge rst)
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if (rst)
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icpu_vpn_r <= #1 {31-`OR1200_IMMU_PS{1'b0}};
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else
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icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS];
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//
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//
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// Physical address is either translated virtual address or
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// Physical address is either translated virtual address or
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// simply equal when IMMU is disabled
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// simply equal when IMMU is disabled
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//
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//
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