| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.12 2003/06/06 02:54:47 lampret
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// Revision 1.12 2003/06/06 02:54:47 lampret
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// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
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// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
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//
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//
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// Revision 1.11 2002/10/17 20:04:40 lampret
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// Revision 1.11 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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| Line 120... |
Line 123... |
// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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// QMEM i/f
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// QMEM i/f
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qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
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qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
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);
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);
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| Line 166... |
Line 169... |
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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input scanb_rst,
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input mbist_si_i;
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scanb_si,
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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scanb_en,
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output mbist_so_o;
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scanb_clk;
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output scanb_so;
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`endif
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`endif
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//
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//
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// IC I/F
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// IC I/F
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//
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//
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| Line 262... |
Line 263... |
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
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assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
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assign icpu_rty_o = qmemimmu_rty_i;
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assign icpu_rty_o = qmemimmu_rty_i;
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assign icpu_err_o = qmemimmu_err_i;
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assign icpu_err_o = qmemimmu_err_i;
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assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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assign scanb_so = scanb_si;
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assign mbist_so_o = mbist_si_i;
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`endif
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`endif
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`else
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`else
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//
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//
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// ITLB SPR access
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// ITLB SPR access
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| Line 395... |
Line 396... |
.sxe(itlb_sxe),
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.sxe(itlb_sxe),
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.ci(itlb_ci),
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.ci(itlb_ci),
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.mbist_si_i(mbist_si_i),
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.scanb_si(scanb_si),
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.mbist_so_o(mbist_so_o),
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.scanb_so(scanb_so),
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.mbist_ctrl_i(mbist_ctrl_i),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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`endif
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// SPR access
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// SPR access
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.spr_cs(itlb_spr_access),
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.spr_cs(itlb_spr_access),
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.spr_write(spr_write),
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.spr_write(spr_write),
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