OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_lsu.v] - Diff between revs 660 and 788

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 660 Rev 788
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2002/02/11 04:33:17  lampret
 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
 
//
// Revision 1.2  2002/01/18 07:56:00  lampret
// Revision 1.2  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
Line 74... Line 77...
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
 
 
module or1200_lsu(
module or1200_lsu(
        // Clock and reset
 
        clk, rst,
 
 
 
        // Internal i/f
        // Internal i/f
        addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
        addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
        du_stall, flushpipe, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
        du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
 
 
        // External i/f to DC
        // External i/f to DC
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
        dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
        dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
);
);
Line 94... Line 95...
//
//
// I/O
// I/O
//
//
 
 
//
//
// Clock and reset
 
//
 
input                           clk;
 
input                           rst;
 
 
 
//
 
// Internal i/f
// Internal i/f
//
//
input   [31:0]                   addrbase;
input   [31:0]                   addrbase;
input   [31:0]                   addrofs;
input   [31:0]                   addrofs;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [dw-1:0]         lsu_datain;
input   [dw-1:0]         lsu_datain;
output  [dw-1:0]         lsu_dataout;
output  [dw-1:0]         lsu_dataout;
output                          lsu_stall;
output                          lsu_stall;
output                          lsu_unstall;
output                          lsu_unstall;
input                           du_stall;
input                           du_stall;
input                           flushpipe;
 
output                          except_align;
output                          except_align;
output                          except_dtlbmiss;
output                          except_dtlbmiss;
output                          except_dmmufault;
output                          except_dmmufault;
output                          except_dbuserr;
output                          except_dbuserr;
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.