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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Diff between revs 869 and 1130

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Rev 869	Rev 1130
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/06/08 16:19:09 lampret`
	`// Added generic flip-flop based memory macro instantiation.`
	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.13 2001/11/20 18:46:15 simons`	`// Revision 1.13 2001/11/20 18:46:15 simons`
`// Break point bug fixed`	`// Break point bug fixed`
Line 344...	Line 347...
`.di_b(rf_dataw)`	`.di_b(rf_dataw)`
`);`	`);`

`else	`else

	`ifdef OR1200_RFRAM_GENERIC

`//`	`//`
`// Instantiation of generic (flip-flop based) register file`	`// Instantiation of generic (flip-flop based) register file`
`//`	`//`
`or1200_rfram_generic rf_a(`	`or1200_rfram_generic rf_a(`
`// Clock and reset`	`// Clock and reset`
Line 369...	Line 374...
`.we_w(rf_we),`	`.we_w(rf_we),`
`.addr_w(rf_addrw),`	`.addr_w(rf_addrw),`
`.di_w(rf_dataw)`	`.di_w(rf_dataw)`
`);`	`);`

	`else

	`//`
	`// RFRAM type not specified`
	`//`
	`initial begin`
	`$display("Define RFRAM type.");`
	`$finish;`
	`end`

	`endif
`endif	`endif
`endif	`endif

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Diff between revs 869 and 1130