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Rev 869 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Break point bug fixed
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// Break point bug fixed
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//
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//
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// Revision 1.12 2001/11/13 10:02:21 lampret
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// Revision 1.12 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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Line 298... |
.do_b()
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.do_b()
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);
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);
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`else
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`else
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`ifdef OR1200_RFRAM_DUALPORT
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//
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//
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// Instantiation of register file two-port RAM A
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// Instantiation of register file two-port RAM A
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//
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//
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or1200_dpram_32x32 rf_a(
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or1200_dpram_32x32 rf_a(
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// Port A
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// Port A
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Line 342... |
.we_b(rf_we),
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.we_b(rf_we),
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.addr_b(rf_addrw),
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.addr_b(rf_addrw),
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.di_b(rf_dataw)
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.di_b(rf_dataw)
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);
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);
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`else
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//
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// Instantiation of generic (flip-flop based) register file
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//
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or1200_rfram_generic rf_a(
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// Clock and reset
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.clk(clk),
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.rst(rst),
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// Port A
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.ce_a(rf_ena),
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.addr_a(rf_addra),
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.do_a(from_rfa),
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// Port B
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.ce_b(rf_enb),
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.addr_b(addrb),
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.do_b(from_rfb),
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// Port W
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.ce_w(rf_we),
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.we_w(rf_we),
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.addr_w(rf_addrw),
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.di_w(rf_dataw)
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);
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`endif
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`endif
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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