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Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8 2001/11/02 18:57:14 lampret
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// Revision 1.8 2001/11/02 18:57:14 lampret
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// Modified virtual silicon instantiations.
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// Modified virtual silicon instantiations.
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//
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//
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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| Line 86... |
Line 89... |
`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_spram_2048x32(
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module or1200_spram_2048x32(
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`ifdef OR1200_BIST
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// RAM BIST
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scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
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`endif
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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clk, rst, ce, we, oe, addr, di, do
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clk, rst, ce, we, oe, addr, di, do
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);
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);
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//
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//
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// Default address and data buses width
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// Default address and data buses width
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//
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//
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parameter aw = 11;
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parameter aw = 11;
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parameter dw = 32;
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parameter dw = 32;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input scanb_rst,
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scanb_si,
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scanb_en,
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scanb_clk;
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output scanb_so;
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`endif
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//
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//
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input rst; // Reset
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Line 130... |
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//
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//
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// Internal wires and registers
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// Internal wires and registers
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//
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//
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`ifdef OR1200_VIRTUALSILICON_SSP
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`else
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`ifdef OR1200_BIST
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assign scanb_so = scanb_si;
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`endif
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`endif
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`ifdef OR1200_ARTISAN_SSP
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`ifdef OR1200_ARTISAN_SSP
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//
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//
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// Instantiation of ASIC memory:
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// Instantiation of ASIC memory:
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Line 210... |
// Virtual Silicon Single-Port Synchronous SRAM
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// Virtual Silicon Single-Port Synchronous SRAM
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//
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//
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`ifdef UNUSED
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`ifdef UNUSED
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vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
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vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
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`else
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`else
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`ifdef OR1200_BIST
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vs_hdsp_2048x32_bist vs_ssp(
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`else
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vs_hdsp_2048x32 vs_ssp(
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vs_hdsp_2048x32 vs_ssp(
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`endif
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`endif
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`endif
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_si),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en),
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.canb_clk(scanb_clk),
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`endif
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.CK(clk),
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.CK(clk),
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.ADR(addr),
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.ADR(addr),
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.DI(di),
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.DI(di),
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.WEN(~we),
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.WEN(~we),
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.CEN(~ce),
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.CEN(~ce),
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