URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32_bw.v] - Diff between revs 1186 and 1194

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1186	Rev 1194
Line 61...	Line 61...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2003/08/26 09:37:02 simons`
	`// Added support for rams with byte write access.`
	`//`
`//`	`//`

`// synopsys translate_off`	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`
Line 377...	Line 380...
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[7:6]),`	`.DI(di[7:6]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we[0]),`	`.WE(we[0]),`
`.DO(do[7:6])`	`.DO(do[7:6])`
	`);`
`//`	`//`
`// Block 4`	`// Block 4`
`//`	`//`
`RAMB4_S2 ramb4_s2_4(`	`RAMB4_S2 ramb4_s2_4(`
`.CLK(clk),`	`.CLK(clk),`
Line 427...	Line 431...
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[15:14]),`	`.DI(di[15:14]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we[1]),`	`.WE(we[1]),`
`.DO(do[15:14])`	`.DO(do[15:14])`
	`);`
`//`	`//`
`// Block 8`	`// Block 8`
`//`	`//`
`RAMB4_S2 ramb4_s2_8(`	`RAMB4_S2 ramb4_s2_8(`
`.CLK(clk),`	`.CLK(clk),`
Line 478...	Line 482...
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[23:22]),`	`.DI(di[23:22]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we[2]),`	`.WE(we[2]),`
`.DO(do[23:22])`	`.DO(do[23:22])`
	`);`
`//`	`//`
`// Block 12`	`// Block 12`
`//`	`//`
`RAMB4_S2 ramb4_s2_12(`	`RAMB4_S2 ramb4_s2_12(`
`.CLK(clk),`	`.CLK(clk),`
Line 528...	Line 533...
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[31:30]),`	`.DI(di[31:30]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we[3]),`	`.WE(we[3]),`
`.DO(do[31:30])`	`.DO(do[31:30])`
	`);`

`else	`else

`//`	`//`
`// Generic single-port synchronous RAM model`	`// Generic single-port synchronous RAM model`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32_bw.v] - Diff between revs 1186 and 1194