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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.6 2002/03/11 01:26:57 lampret
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// Revision 1.6 2002/03/11 01:26:57 lampret
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// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
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// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
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//
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//
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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| Line 101... |
Line 104... |
clk, rst,
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clk, rst,
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// Internal CPU interface
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// Internal CPU interface
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flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,
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flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,
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epcr, eear, esr, except_started,
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epcr, eear, esr, except_started,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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// From/to other RISC units
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// From/to other RISC units
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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| Line 142... |
Line 145... |
output [width-1:0] to_wbmux; // For l.mfspr
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output [width-1:0] to_wbmux; // For l.mfspr
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output epcr_we; // EPCR0 write enable
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output epcr_we; // EPCR0 write enable
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output eear_we; // EEAR0 write enable
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output eear_we; // EEAR0 write enable
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output esr_we; // ESR0 write enable
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output esr_we; // ESR0 write enable
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output pc_we; // PC write enable
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output pc_we; // PC write enable
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output sr_we; // Write enable SR
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output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
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output [`OR1200_SR_WIDTH-1:0] sr; // SR
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output [`OR1200_SR_WIDTH-1:0] sr; // SR
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input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_rf; // Data from RF
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input [31:0] spr_dat_rf; // Data from RF
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input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_ppc; // Data from PPC
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input [31:0] spr_dat_ppc; // Data from PPC
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Line 184... |
//
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//
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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reg write_spr; // Write SPR
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reg write_spr; // Write SPR
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reg read_spr; // Read SPR
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reg read_spr; // Read SPR
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reg [width-1:0] to_wbmux; // For l.mfspr
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reg [width-1:0] to_wbmux; // For l.mfspr
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wire sr_we; // Write enable SR
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wire cfgr_sel; // Select for cfg regs
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wire cfgr_sel; // Select for cfg regs
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wire rf_sel; // Select for RF
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wire rf_sel; // Select for RF
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wire npc_sel; // Select for NPC
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wire npc_sel; // Select for NPC
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wire ppc_sel; // Select for PPC
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wire ppc_sel; // Select for PPC
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wire sr_sel; // Select for SR
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wire sr_sel; // Select for SR
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wire epcr_sel; // Select for EPCR0
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wire epcr_sel; // Select for EPCR0
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wire eear_sel; // Select for EEAR0
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wire eear_sel; // Select for EEAR0
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wire esr_sel; // Select for ESR0
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wire esr_sel; // Select for ESR0
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wire [31:0] sys_data; // Read data from system SPRs
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wire [31:0] sys_data; // Read data from system SPRs
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wire [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
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wire du_access; // Debug unit access
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wire du_access; // Debug unit access
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wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
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wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
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reg [31:0] unqualified_cs; // Unqualified chip selects
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reg [31:0] unqualified_cs; // Unqualified chip selects
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//
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//
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Line 282... |
//
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//
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//
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//
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// What to write into SR
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// What to write into SR
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//
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//
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assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : {1'b1, spr_dat_o[`OR1200_SR_WIDTH-2:0]};
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assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr :
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flag_we ? {sr[`OR1200_SR_FO:`OR1200_SR_CY], flagforw, sr[`OR1200_SR_CE:`OR1200_SR_SM]} : {1'b1, spr_dat_o[`OR1200_SR_WIDTH-2:0]};
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//
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//
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// Selects for system SPRs
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// Selects for system SPRs
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//
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//
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assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
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assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
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Line 300... |
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
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assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
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//
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//
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// Write enables for system SPRs
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// Write enables for system SPRs
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//
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//
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assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE);
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assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we;
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assign pc_we = (write_spr && (npc_sel | ppc_sel));
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assign pc_we = (write_spr && (npc_sel | ppc_sel));
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assign epcr_we = (write_spr && epcr_sel);
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assign epcr_we = (write_spr && epcr_sel);
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assign eear_we = (write_spr && eear_sel);
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assign eear_we = (write_spr && eear_sel);
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assign esr_we = (write_spr && esr_sel);
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assign esr_we = (write_spr && esr_sel);
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Line 338... |
sr[`OR1200_SR_DME] <= #1 1'b0;
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sr[`OR1200_SR_DME] <= #1 1'b0;
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sr[`OR1200_SR_IME] <= #1 1'b0;
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sr[`OR1200_SR_IME] <= #1 1'b0;
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end
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end
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else if (sr_we)
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else if (sr_we)
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sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
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sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
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else if (flag_we)
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sr[`OR1200_SR_F] <= #1 flagforw;
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//
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//
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// MTSPR/MFSPR interface
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// MTSPR/MFSPR interface
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//
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//
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always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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