URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Diff between revs 1175 and 1209

Rev 1175	Rev 1209
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.10.4.2 2003/07/11 01:10:35 lampret`
	`// Added three missing wire declarations. No functional changes.`
	`//`
`// Revision 1.10.4.1 2003/07/08 15:36:37 lampret`	`// Revision 1.10.4.1 2003/07/08 15:36:37 lampret`
`// Added embedded memory QMEM.`	`// Added embedded memory QMEM.`
`//`	`//`
`// Revision 1.10 2002/12/08 08:57:56 lampret`	`// Revision 1.10 2002/12/08 08:57:56 lampret`
`// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.`	`// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.`
Line 455...	Line 458...


`//`	`//`
`// Instantiation of Instruction WISHBONE BIU`	`// Instantiation of Instruction WISHBONE BIU`
`//`	`//`
`or1200_wb_biu iwb_biu(`	`or1200_iwb_biu iwb_biu(`
`// RISC clk, rst and clock control`	`// RISC clk, rst and clock control`
`.clk(clk_i),`	`.clk(clk_i),`
`.rst(rst_i),`	`.rst(rst_i),`
`.clmode(clmode_i),`	`.clmode(clmode_i),`