| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10.4.4 2003/12/09 11:46:49 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.10.4.3 2003/12/05 00:08:44 lampret
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// Revision 1.10.4.3 2003/12/05 00:08:44 lampret
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// Fixed instantiation name.
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// Fixed instantiation name.
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//
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//
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// Revision 1.10.4.2 2003/07/11 01:10:35 lampret
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// Revision 1.10.4.2 2003/07/11 01:10:35 lampret
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// Added three missing wire declarations. No functional changes.
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// Added three missing wire declarations. No functional changes.
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| Line 142... |
Line 145... |
`ifdef OR1200_WB_B3
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`ifdef OR1200_WB_B3
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dwb_cti_o, dwb_bte_o,
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dwb_cti_o, dwb_bte_o,
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`endif
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`endif
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// External Debug Interface
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// External Debug Interface
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
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dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
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|
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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| Line 222... |
Line 225... |
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//
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//
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// External Debug Interface
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// External Debug Interface
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//
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//
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input dbg_stall_i; // External Stall Input
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input dbg_stall_i; // External Stall Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [2:0] dbg_op_i; // External Operation Select Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output dbg_bp_o; // Breakpoint Output
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output dbg_bp_o; // Breakpoint Output
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input dbg_stb_i; // External Address/Data Strobe
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input dbg_we_i; // External Write Enable
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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output [dw-1:0] dbg_dat_o; // External Data Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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output dbg_ack_i; // External Data Acknowledge (not WB compatible)
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|
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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| Line 931... |
Line 936... |
.spr_dat_i(spr_dat_cpu),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_o(spr_dat_du),
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.spr_dat_o(spr_dat_du),
|
|
|
// External Debug Interface
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// External Debug Interface
|
.dbg_stall_i(dbg_stall_i),
|
.dbg_stall_i(dbg_stall_i),
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.dbg_dat_i(dbg_dat_i),
|
|
.dbg_adr_i(dbg_adr_i),
|
|
.dbg_op_i(dbg_op_i),
|
|
.dbg_ewt_i(dbg_ewt_i),
|
.dbg_ewt_i(dbg_ewt_i),
|
.dbg_lss_o(dbg_lss_o),
|
.dbg_lss_o(dbg_lss_o),
|
.dbg_is_o(dbg_is_o),
|
.dbg_is_o(dbg_is_o),
|
.dbg_wp_o(dbg_wp_o),
|
.dbg_wp_o(dbg_wp_o),
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.dbg_bp_o(dbg_bp_o),
|
.dbg_bp_o(dbg_bp_o),
|
|
.dbg_stb_i(dbg_stb_i),
|
|
.dbg_we_i(dbg_we_i),
|
|
.dbg_adr_i(dbg_adr_i),
|
|
.dbg_dat_i(dbg_dat_i),
|
.dbg_dat_o(dbg_dat_o)
|
.dbg_dat_o(dbg_dat_o)
|
|
.dbg_ack_o(dbg_ack_o),
|
);
|
);
|
|
|
//
|
//
|
// Programmable interrupt controller
|
// Programmable interrupt controller
|
//
|
//
|
