| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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| Line 323... |
Line 326... |
wire [dw-1:0] du_dat_du;
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wire [dw-1:0] du_dat_du;
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wire du_read;
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wire du_read;
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wire du_write;
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wire du_write;
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wire [12:0] du_except;
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wire [12:0] du_except;
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wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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wire [dw-1:0] du_dat_cpu;
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wire ex_freeze;
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wire ex_freeze;
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wire [31:0] ex_insn;
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wire [31:0] ex_insn;
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wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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| Line 513... |
Line 516... |
.du_dat_du(du_dat_du),
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.du_dat_du(du_dat_du),
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.du_read(du_read),
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.du_read(du_read),
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.du_write(du_write),
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.du_write(du_write),
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.du_dsr(du_dsr),
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.du_dsr(du_dsr),
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.du_except(du_except),
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.du_except(du_except),
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.du_dat_cpu(du_dat_cpu),
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// Connection IMMU and CPU internally
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// Connection IMMU and CPU internally
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.immu_en(immu_en),
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.immu_en(immu_en),
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// Connection DC and CPU
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// Connection DC and CPU
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| Line 542... |
Line 546... |
.sig_tick(sig_tick),
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.sig_tick(sig_tick),
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// SPRs
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// SPRs
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.supv(supv),
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.supv(supv),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dataout(spr_dat_cpu),
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.spr_dat_cpu(spr_dat_cpu),
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.spr_dat_pic(spr_dat_pic),
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.spr_dat_pic(spr_dat_pic),
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.spr_dat_tt(spr_dat_tt),
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.spr_dat_tt(spr_dat_tt),
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.spr_dat_pm(spr_dat_pm),
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.spr_dat_pm(spr_dat_pm),
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.spr_dat_dmmu(spr_dat_dmmu),
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.spr_dat_dmmu(spr_dat_dmmu),
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.spr_dat_immu(spr_dat_immu),
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.spr_dat_immu(spr_dat_immu),
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| Line 649... |
Line 653... |
.du_dsr(du_dsr),
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.du_dsr(du_dsr),
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// DU's access to SPR unit
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// DU's access to SPR unit
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.du_stall(du_stall),
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.du_stall(du_stall),
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.du_addr(du_addr),
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.du_addr(du_addr),
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.du_dat_i(spr_dat_cpu),
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.du_dat_i(du_dat_cpu),
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.du_dat_o(du_dat_du),
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.du_dat_o(du_dat_du),
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.du_read(du_read),
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.du_read(du_read),
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.du_write(du_write),
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.du_write(du_write),
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.du_except(du_except),
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.du_except(du_except),
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