| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.4 2002/02/01 19:56:55 lampret
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// Revision 1.4 2002/02/01 19:56:55 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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| Line 333... |
Line 336... |
wire [dw-1:0] du_dat_cpu;
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wire [dw-1:0] du_dat_cpu;
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wire ex_freeze;
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wire ex_freeze;
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wire [31:0] ex_insn;
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wire [31:0] ex_insn;
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wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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wire [31:0] spr_dat_npc;
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wire [31:0] rf_dataw;
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//
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//
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// Instantiation of Instruction WISHBONE BIU
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// Instantiation of Instruction WISHBONE BIU
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//
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//
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or1200_wb_biu iwb_biu(
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or1200_wb_biu iwb_biu(
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| Line 513... |
Line 519... |
.du_read(du_read),
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.du_read(du_read),
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.du_write(du_write),
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.du_write(du_write),
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.du_dsr(du_dsr),
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.du_dsr(du_dsr),
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.du_except(du_except),
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.du_except(du_except),
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.du_dat_cpu(du_dat_cpu),
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.du_dat_cpu(du_dat_cpu),
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.rf_dataw(rf_dataw),
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// Connection IMMU and CPU internally
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// Connection IMMU and CPU internally
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.immu_en(immu_en),
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.immu_en(immu_en),
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// Connection DC and CPU
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// Connection DC and CPU
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| Line 548... |
Line 556... |
.spr_dat_tt(spr_dat_tt),
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.spr_dat_tt(spr_dat_tt),
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.spr_dat_pm(spr_dat_pm),
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.spr_dat_pm(spr_dat_pm),
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.spr_dat_dmmu(spr_dat_dmmu),
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.spr_dat_dmmu(spr_dat_dmmu),
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.spr_dat_immu(spr_dat_immu),
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.spr_dat_immu(spr_dat_immu),
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.spr_dat_du(spr_dat_du),
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.spr_dat_du(spr_dat_du),
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.spr_dat_npc(spr_dat_npc),
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.spr_cs(spr_cs),
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.spr_cs(spr_cs),
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.spr_we(spr_we)
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.spr_we(spr_we)
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);
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);
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//
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//
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| Line 640... |
Line 649... |
.ex_freeze(ex_freeze),
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.ex_freeze(ex_freeze),
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.branch_op(branch_op),
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.branch_op(branch_op),
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.ex_insn(ex_insn),
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.ex_insn(ex_insn),
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.du_dsr(du_dsr),
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.du_dsr(du_dsr),
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// For Trace buffer
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.spr_dat_npc(spr_dat_npc),
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.rf_dataw(rf_dataw),
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// DU's access to SPR unit
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// DU's access to SPR unit
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.du_stall(du_stall),
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.du_stall(du_stall),
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.du_addr(du_addr),
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.du_addr(du_addr),
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.du_dat_i(du_dat_cpu),
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.du_dat_i(du_dat_cpu),
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.du_dat_o(du_dat_du),
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.du_dat_o(du_dat_du),
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