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Rev 895 |
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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Added wb_cyc_o assignment after it was removed by accident.
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// Added wb_cyc_o assignment after it was removed by accident.
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//
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//
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// Revision 1.11 2001/11/20 21:28:10 lampret
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// Revision 1.11 2001/11/20 21:28:10 lampret
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// Added optional sampling of inputs.
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// Added optional sampling of inputs.
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_cyc_o <= #1 1'b0;
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wb_cyc_o <= #1 1'b0;
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else
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else
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`ifdef OR1200_NO_BURSTS
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i;
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`else
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i | biu_cab_i;
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i | biu_cab_i;
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`endif
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`else
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`ifdef OR1200_NO_BURSTS
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assign wb_cyc_o = biu_cyc_i;
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`else
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`else
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assign wb_cyc_o = biu_cyc_i | biu_cab_i;
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assign wb_cyc_o = biu_cyc_i | biu_cab_i;
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`endif
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`endif
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`endif
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//
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//
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// WB stb_o
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// WB stb_o
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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