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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Diff between revs 504 and 895

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Rev 504	Rev 895
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/01/03 08:16:15 lampret`
	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
	`//`
`// Revision 1.7 2001/10/21 17:57:16 lampret`	`// Revision 1.7 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
`//`	`//`
`// Revision 1.6 2001/10/14 13:12:10 lampret`	`// Revision 1.6 2001/10/14 13:12:10 lampret`
`// MP3 version.`	`// MP3 version.`
Line 62...	Line 65...
`include "timescale.v"	`include "timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`
`include "or1200_defines.v"	`include "or1200_defines.v"

`ifdef OR1200_XILINX_RAM32X1D	`ifdef OR1200_XILINX_RAM32X1D
	`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
	`module or1200_xcv_ram32x8d`
	`(`
	`DPO,`
	`SPO,`
	`A,`
	`D,`
	`DPRA,`
	`WCLK,`
	`WE`
	`);`
	`output [7:0] DPO;`
	`output [7:0] SPO;`
	`input [4:0] A;`
	`input [4:0] DPRA;`
	`input [7:0] D;`
	`input WCLK;`
	`input WE;`

	`wire [7:0] DPO_0;`
	`wire [7:0] SPO_0;`

	`wire [7:0] DPO_1;`
	`wire [7:0] SPO_1;`

	`wire WE_0 ;`
	`wire WE_1 ;`

	`assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;`
	`assign SPO = A[4] ? SPO_1 : SPO_0 ;`

	`assign WE_0 = !A[4] && WE ;`
	`assign WE_1 = A[4] && WE ;`

	`RAM16X1D ram32x1d_0_0(`
	`.DPO(DPO_0[0]),`
	`.SPO(SPO_0[0]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[0]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_0)`
	`);`

	`//`
	`// Instantiation of block 1`
	`//`
	`RAM16X1D ram32x1d_0_1(`
	`.DPO(DPO_0[1]),`
	`.SPO(SPO_0[1]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[1]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_0)`
	`);`

	`//`
	`// Instantiation of block 2`
	`//`
	`RAM16X1D ram32x1d_0_2(`
	`.DPO(DPO_0[2]),`
	`.SPO(SPO_0[2]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[2]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_0)`
	`);`

	`//`
	`// Instantiation of block 3`
	`//`
	`RAM16X1D ram32x1d_0_3(`
	`.DPO(DPO_0[3]),`
	`.SPO(SPO_0[3]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[3]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_0)`
	`);`

	`//`
	`// Instantiation of block 4`
	`//`
	`RAM16X1D ram32x1d_0_4(`
	`.DPO(DPO_0[4]),`
	`.SPO(SPO_0[4]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[4]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_0)`
	`);`

	`//`
	`// Instantiation of block 5`
	`//`
	`RAM16X1D ram32x1d_0_5(`
	`.DPO(DPO_0[5]),`
	`.SPO(SPO_0[5]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[5]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_0)`
	`);`

	`//`
	`// Instantiation of block 6`
	`//`
	`RAM16X1D ram32x1d_0_6(`
	`.DPO(DPO_0[6]),`
	`.SPO(SPO_0[6]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[6]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_0)`
	`);`

	`//`
	`// Instantiation of block 7`
	`//`
	`RAM16X1D ram32x1d_0_7(`
	`.DPO(DPO_0[7]),`
	`.SPO(SPO_0[7]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[7]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_0)`
	`);`

	`RAM16X1D ram32x1d_1_0(`
	`.DPO(DPO_1[0]),`
	`.SPO(SPO_1[0]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[0]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_1)`
	`);`

	`//`
	`// Instantiation of block 1`
	`//`
	`RAM16X1D ram32x1d_1_1(`
	`.DPO(DPO_1[1]),`
	`.SPO(SPO_1[1]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[1]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_1)`
	`);`

	`//`
	`// Instantiation of block 2`
	`//`
	`RAM16X1D ram32x1d_1_2(`
	`.DPO(DPO_1[2]),`
	`.SPO(SPO_1[2]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[2]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_1)`
	`);`

	`//`
	`// Instantiation of block 3`
	`//`
	`RAM16X1D ram32x1d_1_3(`
	`.DPO(DPO_1[3]),`
	`.SPO(SPO_1[3]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[3]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_1)`
	`);`

	`//`
	`// Instantiation of block 4`
	`//`
	`RAM16X1D ram32x1d_1_4(`
	`.DPO(DPO_1[4]),`
	`.SPO(SPO_1[4]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[4]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_1)`
	`);`

	`//`
	`// Instantiation of block 5`
	`//`
	`RAM16X1D ram32x1d_1_5(`
	`.DPO(DPO_1[5]),`
	`.SPO(SPO_1[5]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[5]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_1)`
	`);`

	`//`
	`// Instantiation of block 6`
	`//`
	`RAM16X1D ram32x1d_1_6(`
	`.DPO(DPO_1[6]),`
	`.SPO(SPO_1[6]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[6]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_1)`
	`);`

	`//`
	`// Instantiation of block 7`
	`//`
	`RAM16X1D ram32x1d_1_7(`
	`.DPO(DPO_1[7]),`
	`.SPO(SPO_1[7]),`
	`.A0(A[0]),`
	`.A1(A[1]),`
	`.A2(A[2]),`
	`.A3(A[3]),`
	`.D(D[7]),`
	`.DPRA0(DPRA[0]),`
	`.DPRA1(DPRA[1]),`
	`.DPRA2(DPRA[2]),`
	`.DPRA3(DPRA[3]),`
	`.WCLK(WCLK),`
	`.WE(WE_1)`
	`);`
	`endmodule`

	`else

`module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`	`module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`

`//`	`//`
`// I/O`	`// I/O`
Line 245...	Line 582...
`.WCLK(WCLK),`	`.WCLK(WCLK),`
`.WE(WE)`	`.WE(WE)`
`);`	`);`

`endmodule`	`endmodule`
	`endif
`endif	`endif

`No newline at end of file`	`No newline at end of file`

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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Diff between revs 504 and 895