| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.4 2002/01/18 14:21:43 lampret
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// Revision 1.4 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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// Fixed 'the NPC single-step fix'.
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//
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//
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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| Line 122... |
Line 125... |
icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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immu_en,
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immu_en,
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// Debug unit
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// Debug unit
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ex_insn, ex_freeze, branch_op,
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ex_insn, ex_freeze, branch_op,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_except,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_except, du_dat_cpu,
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// Data interface
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// Data interface
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dc_en,
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dc_en,
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dcpu_adr_o, dcpu_cyc_o, dcpu_stb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_adr_o, dcpu_cyc_o, dcpu_stb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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| Line 134... |
Line 137... |
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// Interrupt & tick exceptions
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// Interrupt & tick exceptions
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sig_int, sig_tick,
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sig_int, sig_tick,
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// SPR interface
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// SPR interface
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supv, spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm,
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supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
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spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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| Line 186... |
Line 189... |
input [dw-1:0] du_dat_du;
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input [dw-1:0] du_dat_du;
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input du_read;
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input du_read;
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input du_write;
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input du_write;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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output [12:0] du_except;
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output [12:0] du_except;
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output [dw-1:0] du_dat_cpu;
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//
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//
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// Data (DC) interface
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// Data (DC) interface
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//
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//
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output [31:0] dcpu_adr_o;
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output [31:0] dcpu_adr_o;
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| Line 220... |
Line 224... |
input [dw-1:0] spr_dat_pm;
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input [dw-1:0] spr_dat_pm;
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input [dw-1:0] spr_dat_dmmu;
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input [dw-1:0] spr_dat_dmmu;
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input [dw-1:0] spr_dat_immu;
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input [dw-1:0] spr_dat_immu;
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input [dw-1:0] spr_dat_du;
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input [dw-1:0] spr_dat_du;
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output [dw-1:0] spr_addr;
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output [dw-1:0] spr_addr;
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output [dw-1:0] spr_dataout;
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output [dw-1:0] spr_dat_cpu;
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output [31:0] spr_cs;
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output [31:0] spr_cs;
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output spr_we;
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output spr_we;
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//
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//
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// Interrupt exceptions
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// Interrupt exceptions
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| Line 380... |
Line 384... |
.lr_restor(operand_b),
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.lr_restor(operand_b),
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.flag(flag),
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.flag(flag),
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.taken(branch_taken),
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.taken(branch_taken),
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.binsn_addr(lr_sav),
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.binsn_addr(lr_sav),
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.epcr(epcr),
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.epcr(epcr),
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.spr_dat_i(spr_dataout),
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.spr_dat_i(spr_dat_cpu),
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.spr_pc_we(pc_we),
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.spr_pc_we(pc_we),
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.genpc_refetch(genpc_refetch),
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.genpc_refetch(genpc_refetch),
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.genpc_freeze(genpc_freeze),
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.genpc_freeze(genpc_freeze),
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.flushpipe(flushpipe),
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.flushpipe(flushpipe),
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.no_more_dslot(no_more_dslot)
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.no_more_dslot(no_more_dslot)
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| Line 482... |
Line 486... |
.rdb(rf_rdb),
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.rdb(rf_rdb),
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.datab(rf_datab),
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.datab(rf_datab),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
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.spr_write(spr_we),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dataout),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_o(spr_dat_rf)
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.spr_dat_o(spr_dat_rf)
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);
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);
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//
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//
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// Instantiation of operand muxes
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// Instantiation of operand muxes
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| Line 540... |
Line 544... |
.result(mult_mac_result),
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.result(mult_mac_result),
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.mac_stall_r(mac_stall),
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.mac_stall_r(mac_stall),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
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.spr_write(spr_we),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dataout),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_o(spr_dat_mac)
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.spr_dat_o(spr_dat_mac)
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);
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);
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//
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//
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// Instantiation of CPU's SPRS block
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// Instantiation of CPU's SPRS block
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| Line 563... |
Line 567... |
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.du_addr(du_addr),
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.du_addr(du_addr),
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.du_dat_du(du_dat_du),
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.du_dat_du(du_dat_du),
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.du_read(du_read),
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.du_read(du_read),
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.du_write(du_write),
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.du_write(du_write),
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.du_dat_cpu(du_dat_cpu),
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|
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dat_pic(spr_dat_pic),
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.spr_dat_pic(spr_dat_pic),
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.spr_dat_tt(spr_dat_tt),
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.spr_dat_tt(spr_dat_tt),
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.spr_dat_pm(spr_dat_pm),
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.spr_dat_pm(spr_dat_pm),
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| Line 576... |
Line 581... |
.spr_dat_ppc(spr_dat_ppc),
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.spr_dat_ppc(spr_dat_ppc),
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.spr_dat_mac(spr_dat_mac),
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.spr_dat_mac(spr_dat_mac),
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.spr_dat_dmmu(spr_dat_dmmu),
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.spr_dat_dmmu(spr_dat_dmmu),
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.spr_dat_immu(spr_dat_immu),
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.spr_dat_immu(spr_dat_immu),
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.spr_dat_du(spr_dat_du),
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.spr_dat_du(spr_dat_du),
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.spr_dataout(spr_dataout),
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.spr_dat_o(spr_dat_cpu),
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.spr_cs(spr_cs),
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.spr_cs(spr_cs),
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.spr_we(spr_we),
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.spr_we(spr_we),
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.epcr_we(epcr_we),
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.epcr_we(epcr_we),
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.eear_we(eear_we),
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.eear_we(eear_we),
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