OpenCores

Rev 1063	Rev 1200
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/10/17 20:04:40 lampret`
	`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.8 2001/10/21 17:57:16 lampret`	`// Revision 1.8 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
Line 73...	Line 76...
`// Clock and reset`	`// Clock and reset`
`clk, rst,`	`clk, rst,`

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
`endif	`endif

`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, tag_v, tag`	`addr, en, we, datain, tag_v, tag`
`);`	`);`
Line 99...	Line 102...

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
`input scanb_rst,`	`input mbist_si_i;`
`scanb_si,`	input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`scanb_en,`	`output mbist_so_o;`
`scanb_clk;`
`output scanb_so;`
`endif	`endif

`ifdef OR1200_NO_DC	`ifdef OR1200_NO_DC

`//`	`//`
`// Data cache not implemented`	`// Data cache not implemented`
`//`	`//`
`assign tag = {dw-1{1'b0}};`	`assign tag = {dw-1{1'b0}};`
`assign tag_v = 1'b0;`	`assign tag_v = 1'b0;`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`assign scanb_so = scanb_si;`	`assign mbist_so_o = mbist_si_i;`
`endif	`endif

`else	`else

`//`	`//`
Line 130...	Line 131...
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram_512x20 dc_tag0(`	`or1200_spram_512x20 dc_tag0(`
`endif	`endif
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_si_i),`
`.scanb_si(scanb_si),`	`.mbist_so_o(mbist_so_o),`
`.scanb_so(scanb_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we),`	`.we(we),`

Line 42...

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.2  2002/10/17 20:04:40  lampret

// Added BIST scan. Special VS RAMs need to be used to implement BIST.

//

// Revision 1.1  2002/01/03 08:16:15  lampret

// Revision 1.1  2002/01/03 08:16:15  lampret

// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.

// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.

//

//

// Revision 1.8  2001/10/21 17:57:16  lampret

// Revision 1.8  2001/10/21 17:57:16  lampret

// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.

// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.

Line 73...

Line 76...

        // Clock and reset

        // Clock and reset

        clk, rst,

        clk, rst,

`ifdef OR1200_BIST

`ifdef OR1200_BIST

        // RAM BIST

        // RAM BIST

        scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,

        mbist_si_i, mbist_so_o, mbist_ctrl_i,

`endif

`endif

        // Internal i/f

        // Internal i/f

        addr, en, we, datain, tag_v, tag

        addr, en, we, datain, tag_v, tag

);

);

Line 99...

Line 102...

`ifdef OR1200_BIST

`ifdef OR1200_BIST

//

//

// RAM BIST

// RAM BIST

//

//

input                           scanb_rst,

input                           mbist_si_i;

                                scanb_si,

input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control

                                scanb_en,

output                          mbist_so_o;

                                scanb_clk;

output                          scanb_so;

`endif

`endif

`ifdef OR1200_NO_DC

`ifdef OR1200_NO_DC

//

//

// Data cache not implemented

// Data cache not implemented

//

//

assign tag = {dw-1{1'b0}};

assign tag = {dw-1{1'b0}};

assign tag_v = 1'b0;

assign tag_v = 1'b0;

`ifdef OR1200_BIST

`ifdef OR1200_BIST

assign scanb_so = scanb_si;

assign mbist_so_o = mbist_si_i;

`endif

`endif

`else

`else

//

//

Line 130...

Line 131...

`ifdef OR1200_DC_1W_8KB

`ifdef OR1200_DC_1W_8KB

or1200_spram_512x20 dc_tag0(

or1200_spram_512x20 dc_tag0(

`endif

`endif

`ifdef OR1200_BIST

`ifdef OR1200_BIST

        // RAM BIST

        // RAM BIST

        .scanb_rst(scanb_rst),

        .mbist_si_i(mbist_si_i),

        .scanb_si(scanb_si),

        .mbist_so_o(mbist_so_o),

        .scanb_so(scanb_so),

        .mbist_ctrl_i(mbist_ctrl_i),

        .scanb_en(scanb_en),

        .scanb_clk(scanb_clk),

`endif

`endif

        .clk(clk),

        .clk(clk),

        .rst(rst),

        .rst(rst),

        .ce(en),

        .ce(en),

        .we(we),

        .we(we),

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[/] [or1k/] [tags/] [rel_27/] [or1200/] [rtl/] [verilog/] [or1200_dc_tag.v] - Diff between revs 1063 and 1200