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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12.4.2 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.12.4.1 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.12 2002/09/07 05:42:02 lampret
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// Revision 1.12 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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//
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// Revision 1.11 2002/08/28 01:44:25 lampret
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// Revision 1.11 2002/08/28 01:44:25 lampret
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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| Line 145... |
Line 151... |
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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immu_en,
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immu_en,
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// Debug unit
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// Debug unit
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ex_insn, ex_freeze, branch_op,
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ex_insn, ex_freeze, id_pc, branch_op,
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spr_dat_npc, rf_dataw,
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spr_dat_npc, rf_dataw,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_except, du_dat_cpu,
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du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt,
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du_except, du_dat_cpu,
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// Data interface
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// Data interface
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dc_en,
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dc_en,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
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| Line 201... |
Line 208... |
//
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//
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// Debug interface
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// Debug interface
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//
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//
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output [31:0] ex_insn;
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output [31:0] ex_insn;
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output ex_freeze;
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output ex_freeze;
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output [31:0] id_pc;
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output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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input du_stall;
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input du_stall;
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input [dw-1:0] du_addr;
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input [dw-1:0] du_addr;
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input [dw-1:0] du_dat_du;
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input [dw-1:0] du_dat_du;
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input du_read;
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input du_read;
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input du_write;
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input du_write;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input du_hwbkpt;
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output [12:0] du_except;
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output [12:0] du_except;
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output [dw-1:0] du_dat_cpu;
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output [dw-1:0] du_dat_cpu;
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output [dw-1:0] rf_dataw;
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output [dw-1:0] rf_dataw;
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//
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//
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Line 347... |
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire [31:0] mult_mac_result;
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wire [31:0] mult_mac_result;
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wire mac_stall;
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wire mac_stall;
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wire [12:0] except_stop;
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wire [12:0] except_stop;
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wire genpc_refetch;
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wire genpc_refetch;
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wire genpc_stop_refetch;
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wire rfe;
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wire rfe;
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wire lsu_unstall;
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wire lsu_unstall;
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wire except_align;
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wire except_align;
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wire except_dtlbmiss;
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wire except_dtlbmiss;
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wire except_dmmufault;
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wire except_dmmufault;
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| Line 407... |
Line 415... |
.binsn_addr(lr_sav),
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.binsn_addr(lr_sav),
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.epcr(epcr),
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.epcr(epcr),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_i(spr_dat_cpu),
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.spr_pc_we(pc_we),
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.spr_pc_we(pc_we),
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.genpc_refetch(genpc_refetch),
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.genpc_refetch(genpc_refetch),
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.genpc_stop_prefetch(genpc_stop_prefetch),
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.genpc_freeze(genpc_freeze),
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.genpc_freeze(genpc_freeze),
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.genpc_stop_prefetch(1'b0),
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.no_more_dslot(no_more_dslot)
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.no_more_dslot(no_more_dslot)
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);
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);
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//
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//
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// Instantiation of instruction fetch block
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// Instantiation of instruction fetch block
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| Line 431... |
Line 439... |
.if_pc(if_pc),
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.if_pc(if_pc),
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.flushpipe(flushpipe),
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.flushpipe(flushpipe),
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.if_stall(if_stall),
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.if_stall(if_stall),
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.no_more_dslot(no_more_dslot),
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.no_more_dslot(no_more_dslot),
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.genpc_refetch(genpc_refetch),
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.genpc_refetch(genpc_refetch),
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.genpc_stop_prefetch(genpc_stop_prefetch),
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.rfe(rfe),
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.rfe(rfe),
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.except_itlbmiss(except_itlbmiss),
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.except_itlbmiss(except_itlbmiss),
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.except_immufault(except_immufault),
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.except_immufault(except_immufault),
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.except_ibuserr(except_ibuserr)
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.except_ibuserr(except_ibuserr)
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);
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);
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| Line 480... |
Line 487... |
.no_more_dslot(no_more_dslot),
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.no_more_dslot(no_more_dslot),
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.ex_void(ex_void),
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.ex_void(ex_void),
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.id_macrc_op(id_macrc_op),
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.id_macrc_op(id_macrc_op),
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.ex_macrc_op(ex_macrc_op),
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.ex_macrc_op(ex_macrc_op),
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.rfe(rfe),
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.rfe(rfe),
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.du_hwbkpt(du_hwbkpt),
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.except_illegal(except_illegal)
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.except_illegal(except_illegal)
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);
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);
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//
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//
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// Instantiation of register file
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// Instantiation of register file
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| Line 727... |
Line 735... |
.id_freeze(id_freeze),
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.id_freeze(id_freeze),
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.ex_freeze(ex_freeze),
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.ex_freeze(ex_freeze),
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.wb_freeze(wb_freeze),
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.wb_freeze(wb_freeze),
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.if_stall(if_stall),
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.if_stall(if_stall),
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.if_pc(if_pc),
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.if_pc(if_pc),
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.id_pc(id_pc),
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.lr_sav(lr_sav),
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.lr_sav(lr_sav),
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.flushpipe(flushpipe),
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.flushpipe(flushpipe),
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.extend_flush(extend_flush),
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.extend_flush(extend_flush),
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.except_type(except_type),
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.except_type(except_type),
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.except_start(except_start),
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.except_start(except_start),
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