OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Diff between revs 1267 and 1284

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1267 Rev 1284
Line 43... Line 43...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.14  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
//
// Revision 1.12.4.2  2004/02/11 01:40:11  lampret
// Revision 1.12.4.2  2004/02/11 01:40:11  lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
//
// Revision 1.12.4.1  2003/12/09 11:46:48  simons
// Revision 1.12.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
Line 305... Line 308...
wire    [dw-1:0]         lsu_dataout;
wire    [dw-1:0]         lsu_dataout;
wire    [dw-1:0]         sprs_dataout;
wire    [dw-1:0]         sprs_dataout;
wire    [31:0]                   lsu_addrofs;
wire    [31:0]                   lsu_addrofs;
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
 
wire    [4:0]                    cust5_op;
 
wire    [5:0]                    cust5_limm;
wire                            flushpipe;
wire                            flushpipe;
wire                            extend_flush;
wire                            extend_flush;
wire                            branch_taken;
wire                            branch_taken;
wire                            flag;
wire                            flag;
wire                            flagforw;
wire                            flagforw;
Line 476... Line 481...
        .branch_addrofs(branch_addrofs),
        .branch_addrofs(branch_addrofs),
        .lsu_addrofs(lsu_addrofs),
        .lsu_addrofs(lsu_addrofs),
        .sel_a(sel_a),
        .sel_a(sel_a),
        .sel_b(sel_b),
        .sel_b(sel_b),
        .lsu_op(lsu_op),
        .lsu_op(lsu_op),
 
        .cust5_op(cust5_op),
 
        .cust5_limm(cust5_limm),
        .multicycle(multicycle),
        .multicycle(multicycle),
        .spr_addrimm(spr_addrimm),
        .spr_addrimm(spr_addrimm),
        .wbforw_valid(wbforw_valid),
        .wbforw_valid(wbforw_valid),
        .sig_syscall(sig_syscall),
        .sig_syscall(sig_syscall),
        .sig_trap(sig_trap),
        .sig_trap(sig_trap),
Line 548... Line 555...
        .mult_mac_result(mult_mac_result),
        .mult_mac_result(mult_mac_result),
        .macrc_op(ex_macrc_op),
        .macrc_op(ex_macrc_op),
        .alu_op(alu_op),
        .alu_op(alu_op),
        .shrot_op(shrot_op),
        .shrot_op(shrot_op),
        .comp_op(comp_op),
        .comp_op(comp_op),
 
        .cust5_op(cust5_op),
 
        .cust5_limm(cust5_limm),
        .result(alu_dataout),
        .result(alu_dataout),
        .flagforw(flagforw),
        .flagforw(flagforw),
        .flag_we(flag_we),
        .flag_we(flag_we),
        .cyforw(cyforw),
        .cyforw(cyforw),
        .cy_we(cy_we),
        .cy_we(cy_we),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.