| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.12 2001/11/30 18:58:00 simons
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// Revision 1.12 2001/11/30 18:58:00 simons
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// Trap insn couses break after exits ex_insn.
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// Trap insn couses break after exits ex_insn.
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| Line 224... |
Line 227... |
//
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//
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always @(du_except) begin
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always @(du_except) begin
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except_stop = 14'b0000_0000_0000;
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except_stop = 14'b0000_0000_0000;
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casex (du_except)
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casex (du_except)
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13'b1_xxxx_xxxx_xxxx: begin
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13'b1_xxxx_xxxx_xxxx: begin
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except_stop[`OR1200_DU_DRR_HPINTE] = 1'b1;
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except_stop[`OR1200_DU_DRR_IE] = 1'b1;
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end
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end
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13'b0_1xxx_xxxx_xxxx: begin
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13'b0_1xxx_xxxx_xxxx: begin
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except_stop[`OR1200_DU_DRR_IME] = 1'b1;
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except_stop[`OR1200_DU_DRR_IME] = 1'b1;
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end
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end
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13'b0_01xx_xxxx_xxxx:
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13'b0_01xx_xxxx_xxxx:
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| Line 247... |
Line 250... |
13'b0_0000_001x_xxxx:
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13'b0_0000_001x_xxxx:
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except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
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except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
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13'b0_0000_0001_xxxx:
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13'b0_0000_0001_xxxx:
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except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
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except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
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13'b0_0000_0000_1xxx:
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13'b0_0000_0000_1xxx:
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except_stop[`OR1200_DU_DRR_LPINTE] = 1'b1;
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except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
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13'b0_0000_0000_01xx: begin
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13'b0_0000_0000_01xx: begin
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except_stop[`OR1200_DU_DRR_RE] = 1'b1;
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except_stop[`OR1200_DU_DRR_RE] = 1'b1;
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end
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end
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13'b0_0000_0000_001x: begin
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13'b0_0000_0000_001x: begin
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except_stop[`OR1200_DU_DRR_TE] = 1'b1;
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except_stop[`OR1200_DU_DRR_TE] = 1'b1;
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| Line 271... |
Line 274... |
//
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//
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// Breakpoint activation register
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// Breakpoint activation register
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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// SIMON
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// dbg_bp_r <= #1 1'b1;
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dbg_bp_r <= #1 1'b0;
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dbg_bp_r <= #1 1'b0;
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else if (!ex_freeze)
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else if (!ex_freeze)
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dbg_bp_r <= #1 |except_stop
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dbg_bp_r <= #1 |except_stop
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`ifdef OR1200_DU_DMR1_ST
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`ifdef OR1200_DU_DMR1_ST
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| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
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| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
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// DAMJAN | ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
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`endif
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`endif
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`ifdef OR1200_DU_DMR1_BT
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`ifdef OR1200_DU_DMR1_BT
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// DAMJAN | ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
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|
| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
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| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
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`endif
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`endif
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;
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;
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else
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else
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dbg_bp_r <= #1 |except_stop;
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dbg_bp_r <= #1 |except_stop;
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