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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.4 2002/01/14 21:11:50 lampret
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// Revision 1.4 2002/01/14 21:11:50 lampret
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// Changed alignment exception EPCR. Not tested yet.
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// Changed alignment exception EPCR. Not tested yet.
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//
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//
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// Revision 1.3 2002/01/14 19:09:57 lampret
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// Revision 1.3 2002/01/14 19:09:57 lampret
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// Fixed order of syscall and range exceptions.
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// Fixed order of syscall and range exceptions.
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| Line 118... |
Line 121... |
// Internal i/f
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// Internal i/f
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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except_started, except_stop, has_dslot,
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except_started, except_stop, ex_void,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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esr, sr, lsu_addr
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esr, sr, lsu_addr
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);
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);
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//
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//
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Line 168... |
output extend_flush;
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output extend_flush;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output except_start;
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output except_start;
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output except_started;
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output except_started;
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output [12:0] except_stop;
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output [12:0] except_stop;
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input has_dslot;
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input ex_void;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_npc;
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output [31:0] spr_dat_npc;
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//
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//
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// Internal regs and wires
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// Internal regs and wires
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| Line 201... |
Line 204... |
// Simple combinatorial logic
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// Simple combinatorial logic
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//
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//
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assign except_started = extend_flush & except_start;
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assign except_started = extend_flush & except_start;
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assign lr_sav = ex_pc[31:2];
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assign lr_sav = ex_pc[31:2];
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_npc = has_dslot ? ex_pc : id_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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