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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.8 2002/01/28 01:16:00 lampret
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// Revision 1.8 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.7 2002/01/23 07:52:36 lampret
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// Revision 1.7 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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Line 131... |
clk, rst,
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clk, rst,
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// Internal i/f
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// Internal i/f
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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except_started, except_stop, ex_void,
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except_started, except_stop, ex_void,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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esr, sr, lsu_addr, abort_ex
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esr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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Line 157... |
input sig_trap;
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input sig_trap;
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input sig_itlbmiss;
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input sig_itlbmiss;
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input sig_immufault;
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input sig_immufault;
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input sig_tick;
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input sig_tick;
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input branch_taken;
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input branch_taken;
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input genpc_freeze;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
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input ex_freeze;
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input wb_freeze;
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input wb_freeze;
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input if_stall;
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input if_stall;
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input [31:0] if_pc;
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input [31:0] if_pc;
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Line 185... |
output [12:0] except_stop;
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output [12:0] except_stop;
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input ex_void;
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input ex_void;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_npc;
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output [31:0] spr_dat_npc;
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output abort_ex;
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output abort_ex;
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input icpu_ack_i;
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input icpu_err_i;
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input dcpu_ack_i;
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input dcpu_err_i;
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//
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//
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// Internal regs and wires
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// Internal regs and wires
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//
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//
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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Line 508... |
eear <= #1 datain;
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eear <= #1 datain;
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if (esr_we)
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if (esr_we)
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esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
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esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
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end
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end
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`OR1200_EXCEPTFSM_FLU1:
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`OR1200_EXCEPTFSM_FLU1:
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// if (!if_stall & !id_freeze)
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if (icpu_ack_i | icpu_err_i | genpc_freeze)
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// if (!if_stall | genpc_freeze)
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state <= #1 `OR1200_EXCEPTFSM_FLU2;
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state <= #1 `OR1200_EXCEPTFSM_FLU2;
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`OR1200_EXCEPTFSM_FLU2:
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`OR1200_EXCEPTFSM_FLU2:
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if (except_type == `OR1200_EXCEPT_TRAP) begin
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if (except_type == `OR1200_EXCEPT_TRAP) begin
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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extend_flush <= #1 1'b0;
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extend_flush <= #1 1'b0;
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