URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_ic_tag.v] - Diff between revs 1267 and 1273

Rev 1267	Rev 1273
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2004/04/05 08:29:57 lampret`
	`// Merged branch_qmem into main tree.`
	`//`
`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`	`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`	`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
`//`	`//`
`// Revision 1.3 2002/10/24 22:19:04 mohor`	`// Revision 1.3 2002/10/24 22:19:04 mohor`
`// Signal scanb_eni renamed to scanb_en`	`// Signal scanb_eni renamed to scanb_en`
Line 137...	Line 140...
`else	`else

`//`	`//`
`// Instantiation of TAG RAM block`	`// Instantiation of TAG RAM block`
`//`	`//`
	`ifdef OR1200_IC_1W_512B
	`or1200_spram_32x24 ic_tag0(`
	`endif
`ifdef OR1200_IC_1W_4KB	`ifdef OR1200_IC_1W_4KB
`or1200_spram_256x21 ic_tag0(`	`or1200_spram_256x21 ic_tag0(`
`endif	`endif
`ifdef OR1200_IC_1W_8KB	`ifdef OR1200_IC_1W_8KB
`or1200_spram_512x20 ic_tag0(`	`or1200_spram_512x20 ic_tag0(`