| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7.4.2 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.7 2002/10/17 20:04:40 lampret
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// Revision 1.7 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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//
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// Revision 1.6 2002/03/29 15:16:55 lampret
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// Revision 1.6 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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| Line 104... |
Line 110... |
icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
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icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
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icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
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icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
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// Internal i/f
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// Internal i/f
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ic_en,
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ic_en,
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icimmu_adr_i, icimmu_cycstb_i, icimmu_ci_i,
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icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
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icpu_sel_i, icpu_tag_i,
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icqmem_sel_i, icqmem_tag_i,
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icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o,
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icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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| Line 147... |
Line 153... |
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//
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//
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// Internal I/F
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// Internal I/F
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//
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//
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input ic_en;
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input ic_en;
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input [31:0] icimmu_adr_i;
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input [31:0] icqmem_adr_i;
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input icimmu_cycstb_i;
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input icqmem_cycstb_i;
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input icimmu_ci_i;
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input icqmem_ci_i;
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input [3:0] icpu_sel_i;
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input [3:0] icqmem_sel_i;
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input [3:0] icpu_tag_i;
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input [3:0] icqmem_tag_i;
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output [dw-1:0] icpu_dat_o;
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output [dw-1:0] icqmem_dat_o;
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output icpu_ack_o;
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output icqmem_ack_o;
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output icimmu_rty_o;
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output icqmem_rty_o;
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output icimmu_err_o;
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output icqmem_err_o;
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output [3:0] icimmu_tag_o;
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output [3:0] icqmem_tag_o;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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//
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//
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// SPR access
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// SPR access
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| Line 226... |
Line 232... |
assign icbiu_dat_o = 32'h00000000;
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assign icbiu_dat_o = 32'h00000000;
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//
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//
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// Bypases of the IC when IC is disabled
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// Bypases of the IC when IC is disabled
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//
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//
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assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i;
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assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
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assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i;
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assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
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assign icbiu_we_o = 1'b0;
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assign icbiu_we_o = 1'b0;
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assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icpu_sel_i;
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assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
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assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
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assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
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assign icimmu_rty_o = ~icpu_ack_o & ~icimmu_err_o;
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assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
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assign icimmu_tag_o = icimmu_err_o ? `OR1200_ITAG_BE : icpu_tag_i;
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assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
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//
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//
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// CPU normal and error termination
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// CPU normal and error termination
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//
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//
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assign icpu_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
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assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
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assign icimmu_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
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assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
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//
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//
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// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
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// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
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//
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//
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assign ic_addr = (icfsm_biu_read) ? saved_addr : icimmu_adr_i;
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assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
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//
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//
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// Select between input data generated by LSU or by BIU
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// Select between input data generated by LSU or by BIU
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//
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//
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assign to_icram = icbiu_dat_i;
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assign to_icram = icbiu_dat_i;
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//
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//
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// Select between data generated by ICRAM or passed by BIU
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// Select between data generated by ICRAM or passed by BIU
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//
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//
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assign icpu_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
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assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
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//
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//
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// Tag comparison
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// Tag comparison
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//
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//
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always @(tag or saved_addr or tag_v) begin
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always @(tag or saved_addr or tag_v) begin
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| Line 272... |
Line 278... |
//
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//
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or1200_ic_fsm or1200_ic_fsm(
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or1200_ic_fsm or1200_ic_fsm(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.ic_en(ic_en),
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.ic_en(ic_en),
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.icimmu_cycstb_i(icimmu_cycstb_i),
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.icqmem_cycstb_i(icqmem_cycstb_i),
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.icimmu_ci_i(icimmu_ci_i),
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.icqmem_ci_i(icqmem_ci_i),
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.tagcomp_miss(tagcomp_miss),
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.tagcomp_miss(tagcomp_miss),
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.biudata_valid(icbiu_ack_i),
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.biudata_valid(icbiu_ack_i),
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.biudata_error(icbiu_err_i),
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.biudata_error(icbiu_err_i),
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.start_addr(icimmu_adr_i),
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.start_addr(icqmem_adr_i),
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.saved_addr(saved_addr),
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.saved_addr(saved_addr),
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.icram_we(icram_we),
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.icram_we(icram_we),
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.biu_read(icfsm_biu_read),
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.biu_read(icfsm_biu_read),
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.first_hit_ack(icfsm_first_hit_ack),
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.first_hit_ack(icfsm_first_hit_ack),
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.first_miss_ack(icfsm_first_miss_ack),
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.first_miss_ack(icfsm_first_miss_ack),
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