| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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// MP3 version.
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| Line 67... |
Line 70... |
module or1200_immu_tlb(
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module or1200_immu_tlb(
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// Rst and clk
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// Rst and clk
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clk, rst,
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clk, rst,
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// I/F for translation
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// I/F for translation
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tlb_en, vaddr, hit, ppn, uxe, sxe, ci, done,
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tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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);
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| Line 96... |
Line 99... |
output hit;
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output hit;
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output [31:`OR1200_IMMU_PS] ppn;
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output [31:`OR1200_IMMU_PS] ppn;
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output uxe;
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output uxe;
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output sxe;
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output sxe;
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output ci;
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output ci;
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output done;
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//
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//
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// SPR access
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// SPR access
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//
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//
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input spr_cs;
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input spr_cs;
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| Line 121... |
Line 123... |
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
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wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
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wire tlb_tr_en;
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wire tlb_tr_en;
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wire tlb_tr_we;
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wire tlb_tr_we;
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wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
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wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
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wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
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wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
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reg done;
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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// itlbwYmrX: vpn 31-19 v 0
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// itlbwYmrX: vpn 31-19 v 0
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| Line 160... |
Line 161... |
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//
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//
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// Output to SPRS unit
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// Output to SPRS unit
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//
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//
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assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
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assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
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{vpn, {`OR1200_ITLB_INDXH{1'b1}}, v} :
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// {vpn, {`OR1200_ITLB_INDXH-7{1'b0}}, 2'b11, 5'b00000, v} :
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{vpn, tlb_index, {`OR1200_ITLB_TAGW-1{1'b0}}, v} :
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(spr_cs & !spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
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(spr_cs & !spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
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{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {5{1'b1}}, ci} :
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{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
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32'h00000000;
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32'h00000000;
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//
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//
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// Assign outputs from Match registers
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// Assign outputs from Match registers
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//
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//
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| Line 184... |
Line 186... |
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//
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//
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// Assign to Translate registers inputs
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// Assign to Translate registers inputs
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//
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//
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assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
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assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
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spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
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spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
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spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
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spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
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spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
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spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
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//
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//
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// Generate hit
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// Generate hit
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//
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//
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| Line 200... |
Line 202... |
// spr_addr[5:0].
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// spr_addr[5:0].
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//
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//
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assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
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assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
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//
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//
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// Assert one clock cycle after tlb_en is asserted. Deassert once tlb_en is
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// deasserted.
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//
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always @(posedge clk or posedge rst)
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if (rst)
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done <= #1 1'b0;
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else if (tlb_en)
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done <= #1 1'b1;
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else
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done <= #1 1'b0;
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//
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// Instantiation of ITLB Match Registers
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// Instantiation of ITLB Match Registers
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//
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//
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or1200_spram_64x14 itlb_mr_ram(
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or1200_spram_64x14 itlb_mr_ram(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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