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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12.4.2 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.12.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.12 2003/06/06 02:54:47 lampret
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// Revision 1.12 2003/06/06 02:54:47 lampret
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// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
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// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
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//
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//
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// Revision 1.11 2002/10/17 20:04:40 lampret
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// Revision 1.11 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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Line 129... |
`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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// IC i/f
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// QMEM i/f
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icimmu_rty_i, icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cycstb_o, icimmu_ci_o
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qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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Line 173... |
`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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//
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//
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// IC I/F
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// IC I/F
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//
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//
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input icimmu_rty_i;
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input qmemimmu_rty_i;
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input icimmu_err_i;
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input qmemimmu_err_i;
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input [3:0] icimmu_tag_i;
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input [3:0] qmemimmu_tag_i;
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output [aw-1:0] icimmu_adr_o;
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output [aw-1:0] qmemimmu_adr_o;
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output icimmu_cycstb_o;
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output qmemimmu_cycstb_o;
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output icimmu_ci_o;
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output qmemimmu_ci_o;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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wire itlb_spr_access;
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wire itlb_spr_access;
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Line 259... |
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//
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//
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// Put all outputs in inactive state
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// Put all outputs in inactive state
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//
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//
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assign spr_dat_o = 32'h00000000;
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assign spr_dat_o = 32'h00000000;
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assign icimmu_adr_o = icpu_adr_i;
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assign qmemimmu_adr_o = icpu_adr_i;
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assign icpu_tag_o = icimmu_tag_i;
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assign icpu_tag_o = qmemimmu_tag_i;
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assign icimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
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assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
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assign icpu_rty_o = icimmu_rty_i;
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assign icpu_rty_o = qmemimmu_rty_i;
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assign icpu_err_o = icimmu_err_i;
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assign icpu_err_o = qmemimmu_err_i;
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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assign mbist_so_o = mbist_si_i;
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`endif
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`endif
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`else
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`else
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Line 306... |
// Tags:
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// Tags:
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//
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//
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// OR1200_DTAG_TE - TLB miss Exception
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// OR1200_DTAG_TE - TLB miss Exception
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// OR1200_DTAG_PE - Page fault Exception
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// OR1200_DTAG_PE - Page fault Exception
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//
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//
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assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : icimmu_tag_i;
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assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemimmu_tag_i;
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//
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//
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// icpu_rty_o
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// icpu_rty_o
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//
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//
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// assign icpu_rty_o = !icpu_err_o & icimmu_rty_i;
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// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
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assign icpu_rty_o = icimmu_rty_i | itlb_spr_access & immu_en;
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assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
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//
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//
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// icpu_err_o
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// icpu_err_o
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//
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//
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assign icpu_err_o = miss | fault | icimmu_err_i;
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assign icpu_err_o = miss | fault | qmemimmu_err_i;
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//
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//
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// Assert itlb_en_r after one clock cycle and when there is no
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// Assert itlb_en_r after one clock cycle and when there is no
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// ITLB SPR access
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// ITLB SPR access
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//
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//
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Line 338... |
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//
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//
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// use delayed signals.
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// use delayed signals.
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//
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//
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// assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
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// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
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assign icimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
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assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
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//
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//
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// Cache Inhibit
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// Cache Inhibit
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//
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//
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// Cache inhibit is not really needed for instruction memory subsystem.
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// Cache inhibit is not really needed for instruction memory subsystem.
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// If we would do it, we would do it like this.
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// If we would do it, we would do it like this.
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// assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// However this causes a async combinational loop so we stick to
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// However this causes a async combinational loop so we stick to
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// no cache inhibit.
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// no cache inhibit.
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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//
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//
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// Physical address is either translated virtual address or
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// Physical address is either translated virtual address or
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// simply equal when IMMU is disabled
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// simply equal when IMMU is disabled
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//
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//
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assign icimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
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assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
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//
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//
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// Output to SPRS unit
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// Output to SPRS unit
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//
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//
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assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;
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assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;
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