| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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| Line 154... |
Line 157... |
wire itlb_ci;
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wire itlb_ci;
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wire itlb_done;
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wire itlb_done;
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wire fault;
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wire fault;
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wire miss;
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wire miss;
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reg [31:0] icpu_adr_o;
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reg [31:0] icpu_adr_o;
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reg itlb_en_r;
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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// itlbwYmrX: vpn 31-10 v 0
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// itlbwYmrX: vpn 31-10 v 0
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| Line 228... |
Line 232... |
// icpu_err_o
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// icpu_err_o
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//
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//
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assign icpu_err_o = miss | fault | icimmu_err_i;
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assign icpu_err_o = miss | fault | icimmu_err_i;
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//
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//
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// Assert itlb_en_r after one clock cycle
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//
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always @(posedge clk or posedge rst)
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if (rst)
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itlb_en_r <= #1 1'b0;
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else
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itlb_en_r <= #1 itlb_en;
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//
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// Assert itlb_done one clock cycle after new address is first presented and tlb is enabled.
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// Assert itlb_done one clock cycle after new address is first presented and tlb is enabled.
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//
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//
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assign itlb_done = (icpu_adr_i == icpu_adr_o) & itlb_en;
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assign itlb_done = (icpu_adr_i == icpu_adr_o) & itlb_en_r;
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//
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//
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// use delayed signals.
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// use delayed signals.
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//
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//
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