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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_sb_fifo.v] - Diff between revs 977 and 994

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Rev 977	Rev 994
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/08/18 19:53:08 lampret`
	`// Added store buffer.`
	`//`
`//`	`//`

`// synopsys translate_off`	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`
Line 53...	Line 56...

`module or1200_sb_fifo(`	`module or1200_sb_fifo(`
`clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o`	`clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o`
`);`	`);`

`parameter dw = 32;`	`parameter dw = 68;`
`parameter fw = 2;`	parameter fw = `OR1200_SB_LOG;
`parameter fl = 4;`	parameter fl = `OR1200_SB_ENTRIES;

`//`	`//`
`// FIFO signals`	`// FIFO signals`
`//`	`//`
`input clk_i; // Clock`	`input clk_i; // Clock`
Line 89...	Line 92...
`wr_pntr <= #1 {fw{1'b0}};`	`wr_pntr <= #1 {fw{1'b0}};`
`rd_pntr <= #1 {fw{1'b0}};`	`rd_pntr <= #1 {fw{1'b0}};`
`cntr <= #1 {fw+2{1'b0}};`	`cntr <= #1 {fw+2{1'b0}};`
`dat_o <= #1 {dw{1'b0}};`	`dat_o <= #1 {dw{1'b0}};`
`end`	`end`
`// else if ((wr_i && !full_o) && (rd_i && !empty_o)) begin // FIFO Read and Write`
`else if (wr_i && rd_i) begin // FIFO Read and Write`	`else if (wr_i && rd_i) begin // FIFO Read and Write`
`mem[wr_pntr] <= #1 dat_i;`	`mem[wr_pntr] <= #1 dat_i;`
`if (wr_pntr >= fl-1)`	`if (wr_pntr >= fl-1)`
`wr_pntr <= #1 {fw{1'b0}};`	`wr_pntr <= #1 {fw{1'b0}};`
`else`	`else`
`wr_pntr <= #1 wr_pntr + 1'b1;`	`wr_pntr <= #1 wr_pntr + 1'b1;`
`if (empty_o)`	`if (empty_o) begin`
`dat_o <= #1 dat_i;`	`dat_o <= #1 dat_i;`
`else`	`end`
	`else begin`
`dat_o <= #1 mem[rd_pntr];`	`dat_o <= #1 mem[rd_pntr];`
	`end`
`if (rd_pntr >= fl-1)`	`if (rd_pntr >= fl-1)`
`rd_pntr <= #1 {fw{1'b0}};`	`rd_pntr <= #1 {fw{1'b0}};`
`else`	`else`
`rd_pntr <= #1 rd_pntr + 1'b1;`	`rd_pntr <= #1 rd_pntr + 1'b1;`
`end`	`end`
`else if (wr_i && !full_o) begin // FIFO Write`	`else if (wr_i && !full_o) begin // FIFO Write`
`mem[wr_pntr] <= #1 dat_i;`	`mem[wr_pntr] <= #1 dat_i;`
`cntr <= #1 cntr + 1'b1;`	`cntr <= #1 cntr + 1'b1;`
`empty_o <= #1 1'b0;`	`empty_o <= #1 1'b0;`
`if (cntr >= fl) begin`	`if (cntr >= (fl-1)) begin`
`full_o <= #1 1'b1;`	`full_o <= #1 1'b1;`
`cntr <= #1 fl;`	`cntr <= #1 fl;`
`end`	`end`
`if (wr_pntr >= fl-1)`	`if (wr_pntr >= fl-1)`
`wr_pntr <= #1 {fw{1'b0}};`	`wr_pntr <= #1 {fw{1'b0}};`
Line 122...	Line 126...
`end`	`end`
`else if (rd_i && !empty_o) begin // FIFO Read`	`else if (rd_i && !empty_o) begin // FIFO Read`
`dat_o <= #1 mem[rd_pntr];`	`dat_o <= #1 mem[rd_pntr];`
`cntr <= #1 cntr - 1'b1;`	`cntr <= #1 cntr - 1'b1;`
`full_o <= #1 1'b0;`	`full_o <= #1 1'b0;`
`if (cntr <= 0) begin`	`if (cntr <= 1) begin`
`empty_o <= #1 1'b1;`	`empty_o <= #1 1'b1;`
`cntr <= #1 {fw+2{1'b0}};`	`cntr <= #1 {fw+2{1'b0}};`
`end`	`end`
`if (rd_pntr >= fl-1)`	`if (rd_pntr >= fl-1)`
`rd_pntr <= #1 {fw{1'b0}};`	`rd_pntr <= #1 {fw{1'b0}};`

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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_sb_fifo.v] - Diff between revs 977 and 994